BS 9450:1998

Foreword
      Introduction
      Brief Summary
1 Principles and requirements
      1.1 General matters
      1.2 Test procedures
      1.3 Capability approval and maintenance procedures
      1.4 Inspection to the customers' detail
             specification
      1.5 Controlled environment
2 Guidance on the preparation of customers' detail
      specifications
      2.1 Basic information
      2.2 Quality conformity inspection requirements
      2.3 Certified test records
      2.4 Authentication
3 Requirements for manufacturer's guidance to customers
      3.1 Introduction
      3.2 Circuit technology
      3.3 Materials, construction and packages
      3.4 Policy and information on design data and layout
             rules
      3.5 Quality conformity inspection schedules
      3.6 Screening options
      3.7 Added components
      3.8 Capability qualifying circuits
      3.9 Guidance on the ratings and characteristics which
             the customer should specify
Annex A - Minimum contents of a manufacturer's capability
          manual for thick film integrated circuits
Annex B - Minimum contents of a manufacturer's capability
          manual for thin film integrated circuits
Annex C - Minimum contents of a manufacturer's capability
          manual for monolithic bipolar semiconductors
          integrated circuits
Annex D - Minimum contents of a manufacturer's capability
          manual for monolithic unipolar semiconductor
          integrated circuits
Annex E - Minimum contents of a manufacturer's capability
          manual for film and hybrid circuits for use in
          microwave applications
Annex F - Minimum contents of a manufacturer's capability
          manual for monolithic unipolar gallium arsenide
          analogue integrated circuits
Annex G - Guide to the writing of a customer's detail
          specification for a hybrid circuit
Table 1 - Voltage and current symbols for digital integrated
          circuits
Table 2 - Colour code for identification number
Table 3 - Equivalent values for sampling plans
Table 4 - Dimensional tests
Table 5 - Severity levels for shock test
Table 6 - Severity levels for vibration test
Table 7 - Acceleration values
Table 8 - Immersion conditions
Table 9 - Maximum permitted helium leak rate
Table 10 - Pressurization conditions
Table 11 - Severities to be used for the thermal
           intermittance test
Table 12 - Screening levels, test and inspection
Table 13 - Requirements for substrates used in the
           construction of hybrid and passive film
           integrated circuits
Table 14 - Substrate metallization defects
Table 15 - Film resistor defects
Table 16 - Crossover defects
Table 17 - Solder or alloy mounting of substrate
Table 18 - Organic polymer mounting of substrate
Table 19 - Normal acceptance criteria for solder attachments
Table 20 - Organic polymer attachment
Table 21 - Alloy attachment
Table 22 - Bonds: general (gold ball, wedge and tailless)
Table 23 - Gold ball bonds
Table 24 - Wedge bonds
Table 25 - Tailless (crescent) bonds
Table 26 - Ribbon bonds
Table 27 - Internal lead wires
Table 28 - Package conditions
Table 29 - Minimum bond strengths
Table 30 - Minimum test schedules
Table 31 - Sampling plans (Category A)
Table 32 - Sampling plans (Category B)
Table 33 - Blank CQC specification for thick film, thin film,
           packaged multi-chip and monolithic integrated
           circuits and micro-assemblies
Table 34 - Blank CQC specification for base semiconductor
           integrated circuits (bare dice)
Table 35 - Sampling requirements for small production lots
Table A.1 - Design data to be specified in the manual
Figure 1 - Scheme for custom-built integrated circuits
Figure 2 - Flow chart for the procurement and release of
           custom-built integrated circuits
Figure 3 - Parallel detection circuit
Figure 4 - Example of steady state, reverse bias or power
           test set-up for endurance testing
Figure 5 - Parallel excitation
Figure 6 - Ring oscillator
Figure 7 - Scratch criteria
Figure 8 - Scratch criteria: composite metallization
           conductors only
Figure 9 - Void criteria
Figure 10 - Bonding pad areas
Figure 11 - Thin film resistor contact area
Figure 12 - Trimming requirements for thin and thick film
            resistors
Figure 13 - Trimming requirements for thin and thick film
            resistors (serpentine trim)
Figure 14 - Contact angle between solder and conductor tracks
Figure 15 - Contact angle between solder and conductor tracks
Figure 16 - Allowable solder coverage
Figure 17 - Minimum perimeter of solder
Figure 18 - Coverage of solder fillet
Figure 19 - Minimum allowable wetting of wire circumference
Figure 20 - Solder connection of pins through substrate
Figure 21 - Solder connection of lead frames through substrate
Figure 22 - Minimum acceptable solder coverage of perimeter of
            swaged pin
Figure 23 - Minimum acceptable solder coverage of perimeter of
            crimped pin
Figure 24 - Solder coverage of riser pins through eyelets
Figure 25 - Tailless or crescent bonds
Figure 26 - Conductor adhesion to substrate: peel test
Figure 27 - Minimum bond pulls limits for wires of diameter
            up to 3 x 10-3 inch
Figure 28 - Minimum bond pulls limits for wires of diameter
            of 3 x 10-3 inch to 30 x 10-3 inch
Figure 29 - Compliant interface on contact tool
Figure 30 - Alignment of tools with die
Figure 31 - Choice of die edge for application of contact
            tools
Figure 32 - Minimum die attached strength
Figure 33 - Skeleton flow chart
Figure A.1 - Examples of draft capability abstract for thick
             film passive and hybrid integrated circuits
Figure B.1 - Examples of draft capability abstract for thin
             film passive and hybrid integrated circuits
Figure C.1 - Draft capability abstract
Figure D.1 - Example 1 of a draft capability abstract for
             monolithic unipolar semiconductor integrated
             circuits
Figure D.2 - Example 2 of a draft capability abstract for
             monolithic unipolar semiconductor integrated
             circuits
Figure E.1 - D.1 Example of a draft capability abstract for
             film and hybrid integrated circuits for use in
             microwave applications
Figure F.1 - Example of a draft capability abstract for
             gallium arsenide unipolar analogue integrated
             circuits
Figure G.1 - Inspection schedule
List of references