BS IEC 61508-2 : 2000 AMD 13780
Superseded
A superseded Standard is one, which is fully replaced by another Standard, which is a new edition of the same Standard.
A superseded Standard is one, which is fully replaced by another Standard, which is a new edition of the same Standard.
15-03-2002
23-11-2012
FOREWORD
INTRODUCTION
1 Scope
2 Normative references
3 Definitions and abbreviations
4 Conformance to this standard
5 Documentation
6 Management of functional safety
7 E/E/PES safety lifecycle requirements
7.1 General
7.2 E/E/PES safety requirements specification
7.3 E/E/PES safety validation planning
7.4 E/E/PES design and development
7.5 E/E/PES integration
7.6 E/E/PES operation and maintenance procedures
7.7 E/E/PES safety validation
7.8 E/E/PES modification
7.9 E/E/PES verification
8 Functional safety assessment
Annex A (normative) Techniques and measures for E/E/PE
safety-related systems: control of
failures during operation
A.1 - General
A.2 - Hardware safety integrity
A.3 - Systematic safety integrity
Annex B (normative) Techniques and measures for E/E/PE
safety-related systems: avoidance of
systematic failures during the different
phases of the lifecycle
Annex C (normative) Diagnostic coverage and safe failure
fraction
C.1 - Calculation of diagnostic coverage and safe
failure fraction of a subsystem
C.2 - Determination of diagnostic coverage factors
Bibliography
Figure 1 - Overall framework of IEC 61508
Figure 2 - E/E/PES safety lifecycle (in realisation phase)
Figure 3 - Relationship and scope of IEC 61508-2 and IEC
61508-3
Figure 4 - Relationship between the hardware and software
architectures of programmable electronics
Figure 5 - Example limitation on hardware safety integrity
for a single-channel safety function
Figure 6 - Example limitation on hardware safety integrity
for a multiple-channel safety function
Table 1 - Overview - Realisation phase of the E/E/PES safety
lifecycle
Table 2 - Hardware safety integrity: architectural
constraints on type A safety-related subsystems
Table 3 - Hardware safety integrity: architectural
constraints on type B safety-related subsystems
Table A.1 - Faults or failures to be detected during
operation or to be analysed in the derivation of
safe failure fraction
Table A.2 - Electrical subsystems
Table A.3 - Electronic subsystems
Table A.4 - Processing units
Table A.5 - Invariable memory ranges
Table A.6 - Variable memory ranges
Table A.7 - I/O units and interface (external communication)
Table A.8 - Data paths (internal communication)
Table A.9 - Power supply
Table A.10 - Program sequence (watch-dog)
Table A.11 - Ventilation and heating system (if necessary)
Table A.12 - Clock
Table A.13 - Communication and mass-storage
Table A.14 - Sensors
Table A.15 - Final elements (actuators)
Table A.16 - Techniques and measures to control systematic
failures caused by hardware and software design
Table A.17 - Techniques and measures to control systematic
failures caused by enviornmental stress or
influences
Table A.18 - Techniques and measures to control systematic
operational failures
Table A.19 - Effectiveness of techniques and measures to
control systematic failures
Table B.1 - Recommendations to avoid mistakes during
specification of E/E/PES requirements (see 7.2)
Table B.2 - Recommendations to avoid introducing faults
during E/E/PES design and development (see 7.4)
Table B.3 - Recommendations to avoid faults during E/E/PES
integration (see 7.5)
Table B.4 - Recommendations to avoid faults and failures
during E/E/PES operation and maintenance
procedures (see 7.6)
Table B.5 - Recommendations to avoid faults during E/E/PES
safety validation (see 7.7)
Table B.6 - Effectiveness of techniques and measures to avoid
systematic failures
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