Defines a high-performance 32-bitsynchronous bus standard. Meant to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system. Intended for general purpose applications to optimise block transfers, including protocol for message passing.

This International Standard defines the operation, functions, and attributes of the IEEE 1296 bus standard. This standard defines a high-performance 32-bit synchronous bus standard. The bus standard must have a design-in lifetime of 10 years with backward compatibility. The standard is intended for general purpose applications to optimize block transfers, including protocol for message passing. For real-time applications, the bus will provide a means of ensuring an upper limit to message delivery time. The standard is intended to be compatible with existing IEC mechanical standards (IEC Pub 297-1,1 297-3, and 603-2) with recognition of the need for special front panels to address ESD, EMI, and RFI requirements. Options within the standard will be clearly identified. The standard is intended to support multiple processor modules in a functionally partitioned configuration and heterogeneous processor types in the same system. The standard is intended to support heterogeneous processor types in the same system. Message-passing format and protocol is intended for future migration to a serial system bus.