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IEC TR 62856:2013

Current

Current

The latest, up-to-date edition.

Documentation on design automation subjects - The Bird's-eye View of Design Languages (BVDL)

Available format(s)

Hardcopy , PDF 1 User , PDF 3 Users , PDF 5 Users , PDF 9 Users

Language(s)

English - French

Published date

07-08-2013

FOREWORD
INTRODUCTION
1 Scope
2 Structure and content of the Bird's-eye View
  of Design Languages
3 Use case of the Bird's-eye View of Design
  Languages
4 The Bird's-eye View of Design Languages
  (BVDL), version 1.0

IEC/TR 62856:2013 describes features for existing design languages, as well as for enhancing and newly developing design languages belonging to the defined design processes of System on a chip (SoC) which ranges from system level design, SoC design implementation and verification, IP block creation and analog block design down to interface data preparation for manufacturing. Thirty-three design languages have been chosen and each feature of their latest version as of March 2011 is reflected in this report:
UML, Esterel, Rosetta, SystemC, SystemC-AMS, IBIS, CITI, TouchStone, BSDL, System Verilog, VHDL, Verilog HDL, UPF, CPF, e language, PSL, FSDB, SDC, DEF, Open Access, SDF, GDS II, OASIS, STIL, WGL, Verilog-A, Verilog-AMS, SPICE, VHDL-AMS, LEF, Liberty, CDL and IP-XACT.

DevelopmentNote
Stability Date: 2018 (11/2017)
DocumentType
Technical Report
Pages
42
PublisherName
International Electrotechnical Committee
Status
Current

Standards Relationship
NEN NPR IEC/TR 62856 : 2013 Identical
BS EN 50377-15-1:2011 Identical

IEC TR 63051:2017 Documentation on design automation subjects - Mathematical algorithm hardware description languages for system level modeling and verification (HDLMath)
PD IEC/TR 63051:2017 Documentation on design automation subjects. Mathematical algorithm hardware description languages for system level modeling and verification (HDLMath)

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