ATIS T1.413 : 98 SUPP A 2001

Foreword
1 Scope and purpose
2 Referenced standards
3 Definitions, abbreviations, acronyms and symbols
4 Reference models
5 Transport capacity
6 ATU-C functional characteristics
7 ATU-R functional characteristics
8 Operations and maintenance
9 Initialization
10 On-line adaptation and reconfiguration
11 Loop plant, impairments, and testing
12 Electrical characteristics
13 Physical characteristics
14 Environmental conditions
Annex A - ATU-C and ATU-R state diagrams
Annex B - Power spectral density of crosstalk disturbers
Annex C - Characteristics of test impulse waveform
Annex D - Vendor identification numbers
Annex E - POTS splitter requirements
Annex F - ATU-C Transmitter PSD Mask for Reduced NEXT
Annex G - Characteristics of typical telephone cables
Annex H - Aspects of ADSL systems based on 2048 kbit/s
Annex I - Extended impulse noise tests
Annex J - Cell TC Sublayer interfaces
Annex K - Dynamic Rate Adaptation
Annex L - Full Duplex Autonomous Data Transfer for the eoc
Annex M - ADSL line related performance parameters
Annex N - Summary of changes from Issue 1 to Issue 2
Annex O - Bibliography
Table 1 - Required 32 kbit/s multiples for transport of STM
Table 2 - ADSL downstream system overhead (excluding RS FEC
          redundancy)
Table 3 - ADSL upstream system overhead (excluding RS FEC
          redundancy)
Table 4 - Definition of framing structures
Table 5 - Definition of indicator bits, ATU-C transmitter
          (fast data buffer, downstream direction)
Table 6 - Fast byte format (Fast data buffer)
Table 7 - Sync byte format (Interleaved data buffer)
Table 8 - Overhead functions for full and reduced overhead
          mode with separate fast and sync bytes
Table 9 - Overhead functions for reduced overhead mode with
          merged fast and sync bytes
Table 10 - Minimum FEC coding capabilities for ATU-C
Table 11 - Convolutional interleaving example for N=5, D=2
Table 12 - Dummy byte insertion at interleaver input for S=1/2
Table 13 - Forming the binary word u
Table 14 - Relation between 4-dimensional and 2-dimensional
           cosets
Table 15 - Determining the top 2 bits of X and Y
Table 16 - Mapping of two data bits into a 4-QAM
           constellation point
Table 17 - Fast byte format for synchronization (Fast data
           buffer)
Table 18 - Sync bute format for synchronization (Interleaved
           data buffer)
Table 19 - Minimum FEC coding capabilities for ATU-R
Table 20 - eoc message fields
Table 21 - Eoc message opcodes
Table 22 - ATU-R data registers
Table 23 - eoc messages acceptable at the ATU-R
Table 24 - Meaning of four C-Activate signals
Table 25 - Meaning of R-ACK1 and R-ACK2
Table 26 - Power cut-back: downstream PSD as a function of
           upstream received power
Table 27 - C-RATES1
Table 28 - Assignment of 48 bits of C-MSGS1
Table 29 - C-MSG1 encoding rules for transmit PSD during
           C-REVERB1
Table 30 - R-RATES1
Table 31 - Assignment of 48 bits of R-MSGS1
Table 32 - C-RATES-RA
Table 33 - RRSI fields of C-RATES-RA
Table 34 - Assignment of 48 bits of C-MSGS-RA
Table 35 - Assignment of 32 bits of C-MSGS2
Table 36 - Bit pattern for C-RATES2
Table 37 - Assignment of 80 bits of R-MSG-RA
Table 38 - Bit settings for Maximum Interleaving Depth
Table 39 - Bit pattern for R-RATES-RA
Table 40 - Assignment of 32 bits of R-MSGS2
Table 41 - Bit pattern for R-RATES2
Table 42 - Aoc message headers
Table 43 - Format of the bit swap request message
Table 44 - Bit swap request commands
Table 45 - Format of the extended bit swap request message
Table 46 - Format of the bit swap acknowledge
Table 47 - ATU operating modes for performance evaluation by
           category
Table 48 - Loop sets and maximum rates for category I and II
           testing
Table 49 - Crosstalk tests for category I (downstream)
Table 50 - Crosstalk tests for category I (upsteam)
Table 51 - Crosstalk tests for category II (downstream)
Table 52 - Crosstalk tests for category II (upstream)
Table 53 - Test loops, interferers, and data rates for
           impulse tests for category I
Table 54 - Test loops, interferers, and data rates for
           impulse tests for category II
Table 55 - Test loops, interferers, and data rates for POTS
           tests category I
Table 56 - Test loops, interferers, and data rates for POTS
           tests category II
Table 57 - Minimum test time for crosstalk
Table 58 - Pin assignments for 8-position jack and plug at
           Network Interface
Table 59 - Pin assignments for 8-position jack and plug at
           remote location
Figure 1 - ADSL system reference model
Figure 2 - ATU-C transmitter reference model for STM transport
Figure 3 - ATU-C transmitter reference model for ATM transport
Figure 4 - ATU-R transmitter reference model for STM transport
Figure 5 - ATU-R transmitter reference model for STM transport
Figure 6 - ATU-C functional interfaces to the STM layer at
           the V-C reference point
Figure 7 - ATU-C functional interfaces to the ATM layer at the
           V-C reference point
Figure 8 - ATM cell delineation state machine
Figure 9 - Example implementation of the measurement
Figure 10 - ADSL superframe structure - ATU-C transmitter
Figure 11 - Fast sync byte ("fast" byte) format - ATU-C
            transmitter
Figure 12 - Interleaved sync byte ("sync" byte) format -
            ATU-C transmitter
Figure 13 - Fast data buffer - ATU-C transmitter
Figure 14 - Interleaved data buffer, ATU-C transmitter
Figure 15 - Scrambler
Figure 16 - Tone ordering and bit extraction example (without
            trellis coding)
Figure 17 - Tone ordering and bit extraction example (with
            trellis coding)
Figure 18 - Conversion of u to v and w
Figure 19 - Convolutional encoder
Figure 20 - Constituent 2-dimensional cosets for Wei's code
Figure 21 - Trellis diagram
Figure 22 - Constellation labels for b=2 and b=4
Figure 23 - Expansion of points n into the next larger square
            constellation
Figure 24 - Constellation labels for b=3
Figure 25 - Constellation labels for b=5
Figure 26 - MTPR test
Figure 27 - ATU-C transmitter PSD mask
Figure 28 - ATU-R functional interfaces to the STM layer at
            the T-R reference point
Figure 29 - ATU-R functional interfaces to the ATM layer at
            the T-R reference point
Figure 30 - Fast data buffer - ATU-R transmitter
Figure 31 - Interleaved data buffer - ATU-R transmitter
Figure 32 - ATU-R transmitter PSD mask
Figure 33 - ATU-C state diagram for outstanding eoc messages
Figure 34 - EOC receiver state machine at ATU-R
Figure 35 - EOC receiver state machine at ATU-C
Figure 36 - In-service surveillance of the ADSL link shown
            from standpoint of ATU-C
Figure 37 - Illustration of ADSL Lines
Figure 38 - Overview of initialization
Figure 39 - Timing diagram of activation and acknowledgment
            (9.2-9.3)
Figure 40 - Timing diagram of transceiver training (9.4-9.5)
Figure 41 - Timing diagram of channel analysis (9.6-9.7)
Figure 42 - Timing diagram of exchange
Figure 43 - Timing diagram of the initialization sequence
            (part 1)
Figure 44 - Timing diagram of the initialization sequence
            (part 2 - without RA)
Figure 45 - Timing diagram of the initialization sequence
            (part 2 - with RA)
Figure 46 - Overview of test set-up for downstream testing
Figure 47 - Overview of test set-up for upstream testing
Figure 48 - Test loops
Figure 49 - Test impulse 1
Figure 50 - Test impulse 2
Figure 51 - Laboratory test set-up for measuring downstream
            performance margins
Figure 52 - Laboratory test set-up for measuring upstream
            performance margins
Figure 53 - High impedance crosstalk injection circuit
Figure 54 - Longitudinal balance above 30 kHz measurement
            method (only HPF integrated)
Figure 55 - Longitudinal balance above 30 kHz measurement
            method (HPF and LPF integrated)
Figure 56 - Interface on the customer premises side of the U-R
Figure 57 - House Wiring for external POTS splitter
Figure 58 - Wiring for a remote ATU-R with integrated POTS
            splitter