BS IEC 62050:2005

Withdrawn

VHDL register transfer level (RTL) synthesis

Available format(s)

Hardcopy , PDF

Withdrawn date

06-04-2010

Language(s)

English

Published date

11-07-2005

Publisher

British Standards Institution

FOREWORD
IEEE Introduction
1. Overview
   1.1 Scope
   1.2 Compliance to this standard
   1.3 Terminology
   1.4 Conventions
2. References
3. Definitions and acronyms
   3.1 Definitions
   3.2 Acronyms
4. Predefined types
5. Verification methodology
   5.1 Combinational verification
   5.2 Sequential verification
6. Modeling hardware elements
   6.1 Edge-sensitive sequential logic
   6.2 Level-sensitive sequential logic
   6.3 Three-state logic and busses
   6.4 Combinational logic
   6.5 ROM and RAM memories
7. Pragmas
   7.1 Attributes
   7.2 Metacomments
8. Syntax
   8.1 Design entities and configurations
   8.2 Subprograms and packages
   8.3 Types
   8.4 Declarations
   8.5 Specifications
   8.6 Names
   8.7 Expressions
   8.8 Sequential statements
   8.9 Concurrent statements
   8.10 Scope and visibility
   8.11 Design units and their analysis
   8.12 Elaboration
   8.13 Lexical elements
   8.14 Predefined language environment
Annex A (informative) Syntax summary
Annex B (normative) Synthesis package RTL_ATTRIBUTES
Annex C (informative) List of Participants
Index

Defines a subset of very high-speed integrated circuit hardware description language (VHDL) that ensures portability of VHDL descriptions between register transfer level synthesis tools.

Specifies a standard for use of very high-speed integrated circuit hardware description language (VHDL) to model synthesizable register-transfer level digital logic. A standard syntax and semantics for VHDL register-transfer level synthesis is defined. The subset of the VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL constructs are identified that should be ignored or flagged as errors.

Committee	EPL/501
DevelopmentNote	Supersedes 05/30128332 DC. (11/2005)
DocumentType	Standard
Pages	124
PublisherName	British Standards Institution
Status	Withdrawn

Standards	Relationship
IEC 62050:2005	Identical

IEEE 1164-1993	IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164)
IEC 61691-1-1:2011	Behavioural languages - Part 1-1: VHDL Language Reference Manual
IEEE 1076.3-1997	IEEE Standard VHDL Synthesis Packages

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BS IEC 62050:2005

VHDL register transfer level (RTL) synthesis

Table of Contents

Abstract

Scope

General Product Information

International Equivalents

Standards Referencing This Book

Category

Subcategory