BS ISO/IEC 11573:1994

Section 1: General
1.1 Scope
1.2 Definitions
1.3 Abbreviations and acronyms
1.4 Impact of slips
Section 2: Technical requirements, Synchronization methods
2.1 Technical requirements
2.1.1 Jitter and wander at the input
2.1.1.1 C0 and T0 interfaces (144 kbits/s)
2.1.1.2 C1 and T1 interfaces (1,544 Mbits/s)
2.1.1.3 C2 and T2 interfaces (2,048 Mbits/s)
2.1.2 Jitter and wander at the output
2.1.2.1 C0 and T0 interfaces (144 kbits/s)
2.1.2.2 C1 and T1 interfaces (1,544 Mbits/s)
2.1.2.3 C2 and T2 interfaces (2,048 Mbits/s)
2.1.3 Frequency deviation at the input
2.1.4 Accuracy
2.1.5 Lock range
2.1.6 Phase discontinuity of slave clocks
2.2 Synchronization methods for PISNs
2.2.1 High level concepts
2.2.2 Reference Clock Switching Criteria
2.2.3 Reference Restoral
2.2.4 Timing Reference Interfaces and Alarms
2.2.5 Buffers
22.26 Controls
2.2.7 Slip performance objectives
2.2.8 Strategies
Section 3: Description of the synchronization methods
3.1 Plesiochronous operation
3.2 Synchronization from one input
3.3 Automatic switch over with signalling
3.4 Automatic switch over without signalling
Annexes
A. Choice of clock references
A.1 Choice of reference from public nodes
A.2 Choice of references between private nodes
A.3 Avoidance of Timing Loops
B. Synchronization configuration
B.1 Master Slave configurations (synchronization)
B.2 master-master configuration (split timing)
C. Basis of strategies
C.1 Slip rate
C.2 Allocation of the controlled slips
C.3 Unavailability of the links
C.4 Nodal solutions
C.5 Description of the five options
D. Synchronized Private Network Examples
D.1 Example with a small private network
D.2 Example with a big private network
D.3 Example with two different public clock sources
D.4 Example with a transit node
E. Slave Clock Performance Measurement Guidelines
E.1 Slave Clocks considerations
E.1.2 Ideal Operation
E.1.2 Stressed Operation
E.1.3 Holdover Operation
E.2 Test Configuration Guidelines
E.2.1 Reference Clock
E.2.2 Digital Reference Simulation
E.2.3 Output Timing Signal Recovery
E.3 Test Categories
E.3.1 Ideal Testing
E.3.2 Stress Testing
E.3.3 Holdover Testing
F. Signalling for management of synchronization
F.1 Presentation
F.1.1 Configuration parameters
F.1.2 Reactions of the node
F.1.3 Reference clock switching and restoral
F.2 Description of the states
F.2.1 Initial states
F.2.2 Slave states
F.2.3 Autonomous state
F.2.4 Wait states
F.3 Description of the events
F.3.1 Failure of links
F.3.2 Signalling information
F.3.3 Time out
F.4 SDL representation of the state machine
G. Bibliography