ECMA 369 : 3ED 2008
Current
The latest, up-to-date edition.
MAC-PHY INTERFACE FOR ECMA-368
01-12-2013
1 Scope
2 Conformance
3 References
4 Definitions
5 Notational Conventions
6 Abbreviations and Acronyms
7 Overview
8 Interface Signal Description
8.1 Interface Signal Definitions
8.1.1 Control Interface
8.1.2 Data Interface
8.1.3 CCA Interface
8.1.4 Management Interface
8.2 PHY Operational State
9 Registers
9.1 Bit Ordering and Interpretation
9.2 Register Address Spaces
9.3 Static Parameter Definitions
9.4 Static Parameter Coding
9.5 Dynamic Register Definitions
9.6 Register Map
9.7 Register Set Access Timing
9.7.1 Transmit Control Registers
9.7.2 Receive Control Registers
9.8 TONE-NULLING MAP CONTROL
10 Frame Structures
11 Interface Theory of Operation
11.1 Overview
11.1.1 PHY Reset Protocol
11.1.2 Exit from Sleep State
11.1.3 Normal Operation
11.2 Frame Timing
11.3 Ranging Support
11.4 Transceiver Delay Definitions
11.5 Transceiver Turnaround Times
11.5.1 RX-TX Turnaround Time
11.5.2 TX-RX Turnaround Time
11.6 PREAMBLE CONTROL
11.6.1 Single Frame Transmission and Reception
11.6.2 Burst Mode Transmission
11.6.3 Burst Mode Reception
11.7 Transmit Operation
11.7.1 Data Bus Ownership
11.7.2 Single Frame Transmission Control
11.7.3 Burst Mode Transmission Control
11.7.4 Burst Mode Transmit Error Recovery
11.8 Receive Operation
11.8.1 Data Bus Ownership
11.8.2 Single Frame Reception Control
11.8.3 Burst Mode Reception Control
11.8.4 Burst Mode Reception Error Recovery
11.8.5 Zero Length Frame Reception
11.9 MAC Transmit Abort
11.10 MAC Receive Abort
11.11 Error Conditions
11.11.1 Transmit Error Conditions
11.11.2 Receive Error Conditions
11.12 Clear Channel Assessment
11.12.1 CCA Interface Signals
11.12.2 Operation of the CCA Interface
11.13 Management Interface
11.13.1 Management Interface Signals
11.13.2 Operation of the Management Interface
11.13.3 Examples
Annex A (informative) Electrical Specifications
Annex B (informative) PHY Vendor and Version Coding
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