IEEE 1149.1-2013 REDLINE
Withdrawn
A Withdrawn Standard is one, which is removed from sale, and its unique number can no longer be used. The Standard can be withdrawn and not replaced, or it can be withdrawn and replaced by a Standard with a different number.
Hardcopy , PDF
03-21-2024
English
05-13-2013
1. Overview
2. Normative references
3. Definitions, abbreviations, acronyms, and special
terms
4. Test access port (TAP)
5. Test logic architecture
6. Test logic controllers
7. Instruction register
8. Instructions
9. Test data registers
10. Bypass register
11. Boundary-scan register
12. Device identification register
13. Electronic chip identification (ECID) register
14. Initialization data register
15. Initialization status register
16. TMP status register
17. Reset selection register
18. Conformance and documentation requirements
Annex A (informative) - Example implementation using
level-sensitive design techniques
Annex B (normative) - Boundary Scan Description Language
(BSDL)
Annex C (normative) - Procedural Description Language (PDL)
Annex D (informative) - Integrated examples of BSDL and PDL
Annex E (informative) - Example iApply execution flow
This standard defines test logic that can be included in an integrated circuit to provide standardized approaches to: Testing the interconnections between integrated circuits once they have been assembled onto a printed circuit board or other substrate - Testing the integrated circuit itself - Observing or modifying circuit activity during the components normal operation The test logic consists of a boundary-scan register and other building blocks and is accessed through a test access port (TAP).
| Committee |
Test Technology
|
| DevelopmentNote |
Supersedes IEEE 1149.1B. (09/2001) Supersedes IEEE DRAFT 1149.1. (02/2005)
|
| DocumentType |
Standard
|
| ISBN |
978-0-7381-8263-6
|
| Pages |
444
|
| PublisherName |
Institute of Electrical & Electronics Engineers
|
| Status |
Withdrawn
|
| Supersedes |
| BS EN 62258-5:2006 | Semiconductor die products Requirements for information concerning electrical simulation |
| IEEE 1076-2008 REDLINE | IEEE Standard VHDL Language Reference Manual |
| DEFSTAN 00-76(PT1)/1(2005) : INTERIM | ASAAC STANDARDS - PART 1: PROPOSED STANDARDS FOR COMMON FUNCTIONAL MODULES |
| MIL-HDBK-470 Revision A:1997 | DESIGNING AND DEVELOPING MAINTAINABLE PRODUCTS AND SYSTEMS - VOLUME 1 |
| ARINC 849 : 2017 | DATA LOADING SPECIFICATIONS FOR AIRCRAFT COMPONENTS |
| BS IEC 61691-1-1:2011 | Behavioural languages VHDL Language reference manual |
| IEEE 1505.1-2008 | IEEE Standard for the Common Test Interface Pin Map Configuration for High-Density, Single-Tier Electronics Test Requirements Utilizing IEEE Std 1505 |
| ES 59008-2 : 1999 | DATA REQUIREMENTS FOR SEMICONDUCTOR DIE - PART 2 - VOCABULARY |
| EN 62258-5 : 2006 | SEMICONDUCTOR DIE PRODUCTS - PART 5: REQUIREMENTS FOR INFORMATION CONCERNING ELECTRICAL SIMULATION |
| DEFSTAN 66-031(PT8)/2(2016) : 2016 | REQUIREMENTS FOR ELECTRONIC AND ELECTRICAL TEST AND MEASUREMENT EQUIPMENT - PART 8: REQUIREMENTS FOR AUTOMATIC TEST SYSTEMS UTILISING AN OPEN SYSTEM ARCHITECTURE |
| IPC 2221 GERMAN : B | GENERIC STANDARD ON PRINTED BOARD DESIGN |
| DSCC 12229D:2023 | MICROCIRCUIT, DIGITAL, CMOS, MICROPROCESSOR WITH DECOUPLING CAPACITORS, MONOLITHIC SILICON |
| IEEE 1149.7-2022 | IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture |
| DEFSTAN 00-13/3(1994) : 1994 | REQUIREMENTS FOR THE ACHIEVEMENT OF TESTABILITY IN ELECTRONIC AND ALLIED EQUIPMENT |
| IEEE 1149.8.1-2012 | IEEE Standard for Boundary-Scan-Based Stimulus of Interconnections to Passive and/or Active Components |
| 05/30130553 DC : DRAFT MAR 2005 | IEC 62258-5 ED 1 - SEMICONDUCTOR DIE PRODUCTS - PART 5: REQUIREMENTS FOR INFORMATION CONCERNING ELECTRICAL SIMULATION |
| BS IEC 62528:2007 | Standard testability method for embedded core-based integrated circuits |
| IEEE 1149.6-2003 | IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks |
| I.S. EN 62258-5:2006 | SEMICONDUCTOR DIE PRODUCTS - PART 5: REQUIREMENTS FOR INFORMATION CONCERNING ELECTRICAL SIMULATION |
| I.S. EN 16602-60-02:2014 | SPACE PRODUCT ASSURANCE - ASIC AND FPGA DEVELOPMENT |
| DEFSTAN 00-70(PT1)/1(1997) : 1997 | STANDARD SERVICEABILITY TESTING - PART 1: THE PROCESS FOR THE PREPARATION OF AND REQUIREMENTS AND GUIDANCE FOR, A STANDARD SERVICEABILITY TEST SPECIFICATION |
| IEC TR 61734:2006 | Application of symbols for binary logic and analogue elements |
| IEEE 1671.3-2007 | IEEE Standard for Automatic Test Markup Language (ATML) for Exchanging Automatic Test Information via XML (eXtensible Markup Language): Exchanging UUT (Unit Under Test) Description Information |
| IEEE DRAFT 1149.4 : D25 FEB 99 | DRAFT STANDARD FOR A MIXED-SIGNAL TEST BUS |
| CEI EN 62258-5 : 2007 | SEMICONDUCTOR DIE PRODUCTS - PART 5: REQUIREMENTS FOR INFORMATION CONCERNING ELECTRICAL SIMULATION |
| BS IEC 61671:2012 | IEEE standard for automatic test markup language (ATML) for exchanging automatic test equipment and test information via XML |
| BS ISO 18257:2016 | Space systems. Semiconductor integrated circuits for space applications. Design requirements |
| 15/30303546 DC : 0 | BS ISO 18257 - SPACE SYSTEMS - SEMICONDUCTOR INTEGRATED CIRCUITS OF SPACE APPLICATIONS - DESIGN REQUIREMENTS |
| PD ES 59008-2:1999 | Data requirements for semiconductor die Vocabulary |
| DEFSTAN 00-70(PT1)/2(2013) : 2013 | STANDARD SERVICEABILITY TESTING - PART 1: THE PROCESS FOR THE PREPARATION OF AND REQUIREMENTS AND GUIDANCE FOR, A STANDARD SERVICEABILITY TEST SPECIFICATION |
| IEC 63003:2015 | Standard for the common test interface pin map configuration for high-density, single-tier electronics test requirements utilizing IEEE Std 1505™ |
| IEEE 1149.10-2017 | IEEE Standard for High-Speed Test Access Port and On-Chip Distribution Architecture |
| MIL-HDBK-528 Base Document:2017 | Design For Testability (DFT)for Boundary Scan Diagnostics (BSD) |
| MIL-HDBK-62 Base Document:1996 | DOCUMENTATION OF DIGITAL ELECTRONIC SYSTEMS WITH VHDL |
| IEC 61671:2012 | Automatic Test Markup Language (ATML) for Exchanging Automatic Test Equipment and Test Information via XML |
| PD IEC/TR 61734:2006 | Application of symbols for binary logic and analogue elements |
| BS EN 16602-60-02:2014 | Space product assurance. ASIC and FPGA development |
| IEEE 1904.1-2013 | IEEE Standard for Service Interoperability in Ethernet Passive Optical Networks (SIEPON) |
| TR NWT 000418 : ISSUE 2 | GENERIC RELIABILITY ASSURANCE REQUIREMENTS FOR FIBER OPTIC TRANSPORT SYSTEMS (A MODULE OF RQGR, FR-NWT-000796) |
| ISO 18257:2016 | Space systems — Semiconductor integrated circuits for space applications — Design requirements |
| IEC 62258-5:2006 | Semiconductor die products - Part 5: Requirements for information concerning electrical simulation |
| EN 16602-60-02:2014 | Space product assurance - ASIC and FPGA development |
| IEC 61691-1-1:2011 | Behavioural languages - Part 1-1: VHDL Language Reference Manual |
| BS IEC 63003:2015 | Standard for the common test interface pin map configuration for high-density, single-tier electronics test requirements utilizing IEEE Std 1505<sup>TM</sup> |
| PD IEC/TR 63133:2017 | Semiconductor devices. Scan based ageing level estimation for semiconductor devices |
| IEEE 1500:2007 | TESTABILITY METHOD FOR EMBEDDED CORE-BASED INTEGRATED CIRCUITS |
| IEEE 1687-2014 | IEEE Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device |
| GS SMT 001 : 2.1.1 | SURFACE MOUNT TECHNOLOGY (SMT) REQUIREMENTS FOR EMBEDDED COMMUNICATION MODULES FOR MACHINE TO MACHINE COMMUNICATIONS |
| IEC TR 63133:2017 | Semiconductor devices - Scan based ageing level estimation for semiconductor devices |
| IEC 62528:2007 | Standard Testability Method for Embedded Core-based Integrated Circuits |
| IPC 2221B:2012 | GENERIC STANDARD ON PRINTED BOARD DESIGN |
| IPC 2221 FRENCH : B2012 | GENERIC STANDARD ON PRINTED BOARD DESIGN |
| IEEE 1838-2019 | IEEE Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits |
| IEEE 1149.6-2015 | IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks |
| IEEE 1500-2022 | IEEE Standard Testability Method for Embedded Core-based Integrated Circuits |
| IEEE 1149.4-2010 | IEEE Standard for a Mixed-Signal Test Bus |
| IEEE 1149.8.1-2012 | IEEE Standard for Boundary-Scan-Based Stimulus of Interconnections to Passive and/or Active Components |
| IEEE 1076-2008 REDLINE | IEEE Standard VHDL Language Reference Manual |
| IEEE 1149.6-2003 | IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks |
| IEEE 1451.0 : 2007 | SMART TRANSDUCER INTERFACE FOR SENSORS AND ACTUATORS - COMMON FUNCTIONS, COMMUNICATION PROTOCOLS, AND TRANSDUCER ELECTRONIC DATA SHEET (TEDS) FORMATS |
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