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IEEE 1450.6.2-2014

Current

Current

The latest, up-to-date edition.

IEEE Standard for Memory Modeling in Core Test Language

Available format(s)

Hardcopy , PDF

Language(s)

English

Published date

06-13-2014

1 Overview
2 Normative references
3 Definitions, acronyms, and abbreviations
4 Extensions to IEEE Std 1450.6-2005
5 MemoryRepairblock
6 MemoryPhysicalOrganizationblock
7 Memory CTL Orientation and Capabilities Tutorial

SoC test requires reuse of test data and test structures developed for individual cores (designs) when integrated into larger integrated circuits.

Committee
Test Technology
DocumentType
Standard
ISBN
978-0-7381-8972-7
Pages
74
PublisherName
Institute of Electrical & Electronics Engineers
Status
Current

IEEE 1450.2-2002 IEEE Standard for Extensions to Standard Test Interface Language (STIL) (IEEE Std 1450-1999) for DC Level Specification
IEEE 1364-2005 IEEE Standard for Verilog Hardware Description Language
IEEE 1450.1-2005 IEEE Standard for Extensions to Standard Test Interface Language (STIL) (IEEE Std 1450-1999) for Semiconductor Design Environments
IEEE 1450.2 : 2007 EXTENSIONS TO STANDARD TEST INTERFACE LANGUAGE (STIL) FOR DC LEVEL SPECIFICATION
IEEE 1450 : 2007 STANDARD TEST INTERFACE LANGUAGE (STIL) FOR DIGITAL TEST VECTOR DATA
IEEE 1450-1999 IEEE Standard Test Interface Language (STIL) for Digital Test Vector Data
IEEE 1450.6-2005 IEEE Standard Test Interface Language (STIL) for Digital Test Vector Data-Core Test Language (CTL)

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