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IEEE DRAFT 1076.6 : D1.12A 99

Superseded
Superseded

A superseded Standard is one, which is fully replaced by another Standard, which is a new edition of the same Standard.

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superseded

A superseded Standard is one, which is fully replaced by another Standard, which is a new edition of the same Standard.

DRAFT STANDARD FOR VHDL REGISTER TRANSFER LEVEL SYNTHESIS
Superseded date

03-09-2000

Published date

01-12-2013

Publisher

Institute of Electrical & Electronics Engineers

1 Overview
2 References
3 Definitions
4 Predefined types
5 Verification methodology
6 Modeling hardware elements
7 Pragmas
8 Syntax
Annex A Syntax summary (informative)

Standard defines a means of writing VHDL that guarantees the interoperability of VHDL descriptions between any register transfer level synthesis tools that comply to this standard. Standard defines how the semantics of VHDL shall be used.

DocumentType
Draft
PublisherName
Institute of Electrical & Electronics Engineers
Status
Superseded
SupersededBy

IEEE 1164-1993 IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164)
IEEE 1076.3-1997 IEEE Standard VHDL Synthesis Packages
IEEE 1076-2008 REDLINE IEEE Standard VHDL Language Reference Manual

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