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IEEE DRAFT 1497 : DO.9 MAY 99

Superseded
Superseded

A superseded Standard is one, which is fully replaced by another Standard, which is a new edition of the same Standard.

DRAFT STANDARD FOR STANDARD DELAY FORMAT (SDF) FOR THE ELECTRONIC DESIGN PROCESS
Superseded date

12-14-2001

Published date

01-12-2013

1 Overview
    1.1 Scope
    1.2 Organization of this standard
2 References
3 Conventions
    3.1 Terminology conventions
    3.2 Syntactic conventions
4 SDF in the design process
    4.1 Sharing of timing data
    4.2 Using multiple SDF files in one design
    4.3 Timing data and constraints
    4.4 Timing environments
    4.5 Back-annotation of timing data for design
          analysis
    4.6 Forward-annotation of timing constraints for
          design synthesis
    4.7 Timing models supported by SDF
5 Defining the standard delay format
    5.1 SDF file content
    5.2 Header content
    5.3 Cells
    5.4 Delays
    5.5 Timing checks
    5.6 Labels
    5.7 Timing environment
Annex A - Syntax of SDF
Annex B - SDF file examples

This standard delay format (SDF) already exists as an OVI standard for representing and interpreting timing data for use at any stage of the electronic design process. The ASCII data in the SDF file is represented in a tool and language independent way and includes path delays, timing constraint values, interconnect delays and high level technology parameters.

DocumentType
Draft
PublisherName
Institute of Electrical & Electronics Engineers
Status
Superseded

BS IEC 61691-5:2004 Behavioural langages VITALASIC (application specific integrated circuit) modeling specification
IEC 61691-5:2004 Behavioural languages - Part 5: VITAL ASIC (application specific integrated circuit) modeling specification

IEEE 1364-2005 IEEE Standard for Verilog Hardware Description Language
IEEE 1076-2008 REDLINE IEEE Standard VHDL Language Reference Manual

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