1 The packaging revolution
2 Surface mount packages
3 Implementing surface mount technology
4 Life cycle costs
5 SMT failure mechanisms
6 Failure rate prediction model development
Conclusions
References
Appendices
A SMT failure event data
B SMT field and life test data
C Additional RAC services
Tables
1 Military programs using chip carrier technology
2 Ceramic leadless chip carrier package parasitics
3 Chip carrier availability by pin count
4 Jedec 50-mil center chip carriers
5 The advantages and disadvantages of surface mount
       components
6 Chip carrier application considerations
7 A three-year history of solder joint rework
8 Equipment installation (ballpark costs)
9 Thermal coefficients of expansion of various
       materials
10 Solder alloy data characteristics
11 Package application and construction variables
12 Solder connection application and construction
       variables
13 PWB application and construction variables
14 SMT thermal resistance values
15 Distribution of package failures
16 SMT failure data
Figures
1 The past, present and future impact of SMT
2 The major motivating forces behind SMT
3a Package area comparisons
3b Achievable gate count for a given area vs. the
       number of package pins
4a,b Chip carrier package configurations
4c J-lead package configuration
4d Gull wing or S-shape leads package configurations
4e Small outline integrated circuit (SOIC) package
       configurations
5 Surface mount assembly process
6 Soldering with epoxy
7 Wave soldering of a surface mount assembly
8 Vapor phase soldering
9 Test probes
10 Stress contours of a surface mount assembly
11a Assumed cyclic temperature histories for chip
       carrier and substrate during functional
       operation
11b Illustrations of the variability of material
       expansion properties
12a Failure rate results for epoxy/glass boards
12b Failure rate results for glass/polyimide boards
13a,b Leadless chip carrier solder joint formations
14a Solder height vs. interconnection reliability
14b The reliability effects of chip carrier size and
       solder joint height
15 Torque strength vs. stand-off height
16 Typical component termination showing barrier
       layer to prevent precious metal intermetallic
       compound formation with the solder
17a Harmful effects of gold in eutectic SnPb solder
       (reduced ductility)
17b Harmful effects of gold in eutectic SnPb solder
       (reduced fatigue life)
18 Increase in melting temperature from precious
       metal contamination
19 Comparison of percent failed solder joints versus
       number of cycles on carriers with and without
       entrapped flux
20 Temperature cycling produces unequal heating of
       materials
21 Unconstrained approach - flexible top joint
22 Constraining dielectric substrate - ceramic
23 Constraining dielectric substrate - polymeric
24 The results of the thermal shock tests show that
       a typical polyimide/glass board fails after
       several hundred cycles