ESD TR5.3.2-01 : 2000

1 Purpose
2 Table of Contents
3 Introduction
4 Differences between an "Ideal Socketed CDM" Tester
   and a "Socket Device Model" Tester
5 Socket Device Model (SDM) ESD Test Systems
6 What Do Users of SDM Testers Really Need to Know?
   6.1 Waveform Confirmation
   6.2 Waveform Measurement using Different Bandwidth
        Oscilloscopes
   6.3 An Example of Tester Upgrade Influence on Test
        Measurements
   6.4 SDM Tester Parasitic Capacitance
   6.5 Determining a De-rating Factor when Adding
        Intermediate Boards in the Discharge Path
7 Understanding How An SDM Test System Operates
   7.1 Internal SDM Tester Parasitics
   7.2 The Effect of Internal Parasitics on SDM
        Discharge Waveforms
   7.3 The Effect of Device Capacitance in An SDM Event
   7.4 An Additional Note about Internal IC or On-chip
        Capacitance
8 What Do You Need to Know to Improve SDM Testers ?
   8.1 Internal Tester Parasitics
   8.2 Transmission Line Effects
   8.3 Capacitive Coupling due to High Voltages
9 Ideas Regarding Construction of New Generation
   SDM Testers
10 Conclusion
11 References