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IEEE 1516.4 : 2007

Current

Current

The latest, up-to-date edition.

VERIFICATION, VALIDATION, AND ACCREDITATION OF A FEDERATION - AN OVERLAY TO THE HIGH LEVEL ARCHITECTURE FEDERATION DEVELOPMENT AND EXECUTION PROCESS

Available format(s)

Hardcopy , PDF

Language(s)

English

Published date

01-01-2007

1 Overview
  1.1 Scope
  1.2 Purpose
  1.3 Conventions
2 Normative references
3 Definitions, acronyms, and abbreviations
  3.1 Definitions
  3.2 Special terms
  3.3 Acronyms and abbreviations
4 Federation VV&A roles and responsibilities
5 Overlay assumptions and tailoring
  5.1 Assumptions
  5.2 Tailoring
6 VV&A Overlay model: top-level view
7 VV&A Overlay model: detailed view
  7.1 Phase 1 - Verify federation objectives
  7.2 Phase 2 - Verify and validate federation conceptual model
  7.3 Phase 3 - Verify federation design
  7.4 Phase 4 - Verify federation development products
  7.5 Phase 5 - Validate and accept federation
  7.6 Phase 6 - Verify and validate federation output
  7.7 Phase 7 - Consolidate federation VV&A products
8 Conclusion
Annex A (informative) Bibliography

Describes the processes and procedures that should be followed to implement Verification, Validation, and Accreditation (VV&A) for federations being developed using the High Level Architecture (HLA) Federation Development and Execution Process (FEDEP).

DocumentType
Standard
Pages
76
PublisherName
Institute of Electrical & Electronics Engineers
Status
Current

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