1 Scope
1.1 Scope
1.2 Application
2 Referenced documents
2.1 Issue of documents
3 Definitions
3.1 Bit
3.2 Bit rate
3.3 Pulse Code Modulation (PCM)
3.4 Time Division Multiplexing (TDM)
3.5 Half duplex
3.6 Word
3.7 Message
3.8 Subsystem
3.9 Data bus
3.10 Terminal
3.11 Bus controller
3.12 Bus monitor
3.13 Remote Terminal (RT)
3.14 Asynchronous operation
3.15 Dynamic bus control
3.16 Command/response
3.17 Redundant data bus
3.18 Broadcast
3.19 Mode code
4 General requirements
4.1 Test and operating requirements
4.2 Data bus operation
4.3 Characteristics
4.3.1 Data form
4.3.2 Bit priority
4.3.3 Transmission method
4.4 Terminal operation
4.4.1 Common operation
4.4.2 Bus controller operation
4.4.3 Remote terminal
4.4.4 Bus monitor operation
4.5 Hardware characteristics
4.5.1 Data bus characteristics
4.5.2 Terminal characteristics
4.6 Redundant data bus requirements
4.6.1 Electrical isolation
4.6.2 Single event failures
4.6.3 Dual standby redundant data bus
5 Detail requirements
Figures
1 Sample multiplex data bus architecture
2 Data encoding
3 Word formats
4 Command and status sync
5 Data sync
6 Information transfer formats
7 Broadcast information transfer formats
8 Intermessage gap and response time
9 Data bus interface using trans. coupling
10 Data bus interface using direct coupling
11 Coupling transformer
12 Terminal I/O characteristics for transformer coupled
    and direct coupled stubs
13 Output waveform
Tables
I Assigned mode codes
II Criteria for acceptance or rejection of a terminal
    for the noise rejection test
Appendix
10 General
10.1 Redundancy
10.2 Bus controller
10.3 Multiplex selection criteria
10.4 High reliability requirements
10.5 Stubbing
10.6 Use of broadcast option
20 General
20.1 Mode codes
20.2 Broadcast command
20.3 Mode code indicators
20.3.1 Bus controllers
20.3.2 Remote terminals
20.4 Data bus cable
20.4.1 Shielding
20.4.2 Characteristic impedance
20.5 Cable coupling
20.6 Direct coupled stubs
20.7 Redundant data bus requirements
20.8 Design considerations
20.8.1 Mode code indicator
20.8.2 Clock stability
20.8.3 Response time
Appendix Figures
10.1 Illustration of possible redundancy
10.2 Illustration of possible redundancy