Intellectual Property Rights
Foreword
1 Scope
2 References
3 Definitions, symbols and abbreviations
  3.1 Definitions
  3.2 Symbols
  3.3 Abbreviations
4 Overview
  4.1 The 1394 SSCS
  4.2 HIPERLAN/2 Bus
  4.3 Numbering and coding conventions
5 User plane services
  5.1 General
  5.2 Primitives (informative)
      5.2.1 Primitive types
      5.2.2 Parameter definitions
      5.2.3 Interface to the upper layer
            5.2.3.1 Primitives related to isochronous
                    traffic
            5.2.3.2 Primitives related to asynchronous
                    traffic
      5.2.4 Interface to the common part
  5.3 Clock synchronization service
      5.3.1 General
      5.3.2 Clock SSCS PDU format
      5.3.3 Procedures
            5.3.3.1 Procedure in the wireless cycle master
                    (WCM)
            5.3.3.2 Procedure in a wireless cycle slave
                    (WCS)
  5.4 Asynchronous transaction data transport service
      5.4.1 General
      5.4.2 Asynchronous SSCS PDU coding
      5.4.3 Asynchronous packets management
      5.4.4 Procedures
            5.4.4.1 Procedure in the sender
            5.4.4.2 Procedure in receiver
      5.4.5 Broadcast write transaction specificity
  5.5 Stream data transport service
      5.5.1 Isochronous stream data transport service
            5.5.1.1 General
            5.5.1.2 Isochronous stream SSCS PDU coding
            5.5.1.3 Procedure
      5.5.2 Asynchronous stream data transport service
            5.5.2.1 General
            5.5.2.2 Asynchronous stream SSCS PDU coding
            5.5.2.3 Procedure
6 Control plane services
  6.1 General
  6.2 Primitives (informative)
       6.2.1 CL_CONTROL {request, confirm}
       6.2.2 CL_SELF_ID {indication}
  6.3 Association - Initialization
  6.4 Bus reset service
       6.4.1 General
       6.4.2 Procedures
             6.4.2.1 CC or WT initiated bus reset
             6.4.2.2 Bus reset worst case duration
             6.4.2.3 Procedure in the CC side
             6.4.2.4 Procedure in the WT side
       6.4.3 Assignment of physical_IDs
  6.5 Clock information connection control
       6.5.1 General
       6.5.2 Wireless cycle master procedure
             6.5.2.1 Wireless cycle master election
             6.5.2.2 Wireless cycle master operation
       6.5.3 Wireless cycle slave procedure
       6.5.4 CC specific procedure
  6.6 CL responsibility handover
  6.7 HL2 Address Resolution service (HARP)
       6.7.1 General
       6.7.2 Procedures
             6.7.2.1 Procedure in the sender
             6.7.2.2 Procedure in the receiver
  6.8 Asynchronous transaction connection control service
       6.8.1 Asynchronous transaction mapping to a DLC
             connection
             6.8.1.1 General
             6.8.1.2 Procedures
       6.8.2 Clean closing service
             6.8.2.1 General
             6.8.2.2 Clean closing SSCS PDU format
             6.8.2.3 Procedures
  6.9 Isochronous stream connection control service
       6.9.1 General
       6.9.2 SSCS procedure
             6.9.2.1 General
             6.9.2.2 Procedure at the talker side
             6.9.2.3 Procedure at the listener side
             6.9.2.4 Procedure at the IRM side
  6.10 Asynchronous streams connection control service
       6.10.1 IRM and PCR functions
       6.10.2 Asynchronous stream relaying
              6.10.2.1 General
              6.10.2.2 Procedures
7 Convergence layer specific parameters
  7.1 Convergence layer identifier
  7.2 Convergence layer version
  7.3 Maximum transmission unit
  7.4 Information elements for 1394 SSCS
      7.4.1 Information element format
      7.4.2 Information element type coding
      7.4.3 HARP_REQUEST information element
      7.4.4 HARP_RESPONSE information element
      7.4.5 EUI_64 information element
      7.4.6 CHANNEL information element
      7.4.7 BUS_SUSPEND information element
      7.4.8 BUS_RESUME information element
      7.4.9 BUS_RESET information element
      7.4.10 TRANSACTION_INDICATOR information element
Annex A (normative): HIPERLAN/2 CSRs
      A.1 CSR registers
          A.1.1 Standard CSR registers
          A.1.2 Unimplemented wired-1394 registers
          A.1.3 INTERRUPT_TARGET register
          A.1.4 CYCLE_TIME register
          A.1.5 BUS_TIME register
          A.1.6 LOCAL_CYCLES register
          A.1.7 LOCAL_SECONDS register
          A.1.8 SPLIT_TIMEOUT register
      A.2 PCRs
          A.2.1 oPCR format
          A.2.2 iPCR format
          A.2.3 PCR error codes
      A.3 ROM information
      A.4 Locked messages
          A.4.1 Locked message formats
          A.4.2 ALLOCATE_SOME
          A.4.3 MODIFY_BANDWIDTH
          A.4.4 RECLAIM_THIS
          A.4.5 RELEASE_THIS
Annex B (informative): Quadlet-structured PDU formats
      B.1 Asynchronous subtractions
      B.2 Isochronous streams
      B.3 Asynchronous streams
Annex C (normative): Nonbridge upper layer
      C.1 Primitives (informative)
      C.2 Time stamps for split-response timeouts
          (normative)
      C.3 User plane
          C.3.1 Isochronous stream transport service
          C.3.2 Asynchronous transaction
      C.4 Control plane (normative)
          C.4.1 Clock connection control
          C.4.2 Isochronous stream connection control
Annex D (informative): Bibliography
History