VITA 1 : 1994(S2011)

Abstract
Foreword
VMEbus Specification Geneology
Chapter 1
Introduction to the VMEbus Specification
1.1 VMEbus Specification Objectives
1.2 VMEbus Interface System Elements
1.3 VMEbus Specification Diagrams
1.4 Specification Terminology
1.5 Protocol Specification
1.6 System Examples and Explanations
Chapter 2
Data Transfer Bus
2.1 Introduction
2.2 Data-Transfer Bus Lines
2.3 DTB Modules -- Basic Description
2.4 Typical Operation
2.5 Data-Transfer Bus Acquisition
2.6 DTB Timing Rules and Observations
Chapter 3
Data Transfer Bus Arbitration
3.1 Bus Arbitration Philosophy
3.2 Arbitration Bus Lines
3.3 Functional Modules
3.4 Typical Operation
3.5 Race Conditions Between Master Requests and Arbiter Grants
Chapter 4
Priority Interrupt Bus
4.1 Introduction
4.2 Priority Interrupt Bus Lines
4.3 Priority Interrupt Bus Modules - Basic Description
4.4 Typical Operation
4.5 Race Conditions
4.6 Priority Interrupt Bus Timing Rules and Observations
Chapter 5
Utility Bus
5.1 Introduction
5.2 Utility Bus Signal Lines
5.3 Utility Bus Modules
5.4 System Initialization and Diagnostics
5.5 Power and Ground pins
5.6 Reserved Line
5.7 Auto Slot Id
5.8 Auto System Controller
Chapter 6
Electrical Specifications
6.1 Introduction
6.2 Power Distribution
6.3 Electrical Signal Characteristics
6.4 Bus Driving and Receiving Requirements
6.5 Backplane Signal Line Interconnections
6.6 User Defined Signals
6.7 Signal Line Drivers and Terminations
Chapter 7
Mechanical Specifications
7.1 Introduction
7.2 VMEbus Boards
7.3 Front Panels
7.4 Backplanes
7.5 Assembly of VMEbus Subracks
7.6 Conduction Cooled VMEbus Systems
7.7 VMEbus Backplane Connectors and VMEbus Board Connectors
Appendix A
Glossary of VMEbus Terms
Appendix B
VMEbus Connector/Pin Description
Appendix C
Manufacturer's Board Identification
Appendix D
Rule Index
List of Figures
1-1 System Elements Defined by this Document
2-1 Data Transfer Bus Functional Block Diagram
3-1 Arbitration Functional Block Diagram
4-1 Priority Interrupt Bus Functional Diagram
5-1 Utility Bus Block Diagram
6-1 VMEbus Signal Levels
7-1 Subrack with Mixed Board Sizes
List of Tables
2-1 The Eight Categories of Byte Locations
2-28 Address Alignment on Bus
2-2 Signal Levels During Data Transfers
2-3 Address Modifier Codes
2-4 Use of Data Lines to Move Data During Nonmultiplexed Data
        Transfers
2-29 Use of the Address and Data Lines for Multiplexed Data Cycles
2-5 RULES AND PERMISSIONS That Specify The Use of the Dotted Lines
        by the Various Types of Masters
2-6 Slaves - RULES AND PERMISSIONS That Specify the Use of the
2-7 Use of the BTO () Mnemonic
2-8 Location Monitors - RULES AND PERMISSIONS That Specify the Use
        of the Dotted Lines by the Various Types of Location Monitors
2-9 Mnemonics that Specify Addressing Capabilities
2-10 Mnemonics that Specify Basic Data Transfer Capabilities
2-11 Mnemonics that Specify Block Transfer Capabilities
2-12 The Mnemonic that Specifies Read-Modify-Write Capabilities
2-13 Transferring 32 Bits of Data Using Multiple-Byte Transfer Cycles
2-14 Transferring 16 Bits of Data Using Multiple-Byte Transfer Cycles
2-15 Mnemonic that Specifies Unaligned Transfer Capability
2-16 Mnemonics that Specify Address only Capability
2-30 Configuration ROM/Control & Status Registers
2-31 Control and Status Register Base Definition
2-32 Configuration ROM Definition
2-17 Timing Diagrams That Define Master, Slave and Location Monitor
        Operation (see table 2-22 for timing values)
2-18 Definitions of Mnemonics Used in tables 2-19, 2-20, and 2-21
2-19 Use of the Address and Data Lines to Select A Byte Group
2-20 Use of the DS1*, DSO*,A1, A2, and LWORD* During the Address
        Phase of the
2-21 Use of the Data Lines to Transfer Data
2-22 Master, Slave and Location Monitor Timing Parameters
2-23 Bus-Timer Timing Parameters
2-24 Master,Timing RULEs and OBSERVATIONS
2-25 Slave, Timing RULEs and OBSERVATIONS
2-26 Location Monitor, Timing OBSERVATIONS
2-27 Bus Timer, Timing RULEs
4-1 RULES AND PERMISSIONS that Specify the Use of the Dotted Lines
4-2 RULES AND PERMISSIONS that Specify the Use of the Dotted
4-3 Use of the IH() Mnemonic to Specify Interrupt
4-4 Use of the I() Mnemonic to Specify Interrupt Request
4-5 Mnemonics that Specify Status/Id Transfer Capabilities
4-6 Mnemonics that Specify Interrupt Request Release Capabilities
4-7 3-Bit Interrupt Acknowledge Code
4-8 Timing Diagrams that Define Interrupt Handler and
4-9 Timing Diagrams that Define IACK Daisy-Chain Driver Operation
4-10 Timing Diagrams that Define Participating Interrupter Operation
4-11 Timing Diagrams that Define Responding Interrupter Operation
4-12 Definitions of Mnemonics Used in Tables 4-13, 4-14, and 4-15
4-13 Use of Addressing Lines During Interrupt Acknowledge Cycles
4-14 Use of the DS1*, DSO* LWORD*, and WRITE Lines During
4-15 Use of the data bus lines to transfer the Status/Id
4-16 Interrupt Handler, Interrupter, and IACK DAISY-CHAIN
4-17 Interrupt Handler, Timing RULES AND OBSERVATIONS
4-18 Interrupter, Timing RULES AND OBSERVATIONS
4-19 IACK Daisy-Chain Driver, Timing RULES AND OBSERVATIONS
5-1 Module Drive During Power-Up and Power-Down Sequences
6-1 Bus Voltage Specification
6-2 Bus Driving and Receiving Requirements
6-3 Bus Driver Summary
7-1 J1/P1 Pin Assignments
7-2 J2/P2 Pin Assignments