ANSI INCITS 397 VOL-2 : 2005

Foreword
Introduction
1 Scope
2 Normative references
   2.1 Approved references
   2.2 References under development
   2.3 Other references
3 Definitions, abbreviations, and conventions
   3.1 Definitions and abbreviations
   3.2 Conventions
4 General command operational requirements
5 Interface register descriptions
6 Command descriptions
7 Parallel interface physical and electrical requirements
   7.1 Cable configuration
   7.2 Electrical characteristics
   7.3 Connectors and cable assemblies
   7.4 Physical form factors
8 Parallel interface signal assignments and descriptions
   8.1 Signal summary
   8.2 Signal descriptions
9 Parallel interface general operational requirements
   9.1 Interrupts
   9.2 Multiword DMA
   9.3 Ultra DMA feature set
   9.4 Host determination of cable type by detecting
         CBLID-
10 Parallel interface register addressing
11 Parallel interface transport protocol
   11.1 Power-on and hardware reset protocol
   11.2 Software reset protocol
   11.3 Bus idle protocol
   11.4 Non-data command protocol
   11.5 PIO data-in command protocol
   11.6 PIO data-out command protocol
   11.7 DMA command protocol
   11.8 PACKET command protocol
   11.9 READ/WRITE DMA QUEUED command protocol
   11.10 EXECUTE DEVICE DIAGNOSTIC command protocol
   11.11 DEVICE RESET command protocol
   11.12 Ultra DMA data-in commands
   11.13 Ultra DMA data-out commands
   11.14 Ultra DMA CRC rules
12 Parallel interface timing
   12.1 Deskewing
   12.2 Transfer timing
13 Serial interface overview
14 Serial interface physical layer
15 Serial interface link layer
16 Serial interface transport layer
17 Serial interface device command layer
18 Host command layer
19 Serial interface host adapter register interface
20 Serial interface error handling
Annexes
A Bibliography
B Command Set Summary
C Design and Programming Considerations for Large
  Physical Sector Sizes
D Device Determination of Cable Type
  D.1 Overview
  D.2 Sequence for device detection of installed
      capacitor
  D.3 Using the combination of methods for detecting
      cable type
E Signal Integrity and UDMA Guide
  E.1 Introduction
  E.2 The issues
  E.3 System Guidelines for Ultra DMA
      E.3.1 System capacitance
      E.3.2 Pull-up and pull-down resistors
      E.3.3 Cables and connectors
      E.3.4 Host PCB and IC design
      E.3.5 Sender and recipient component I/Os
  E.4 Ultra DMA electrical characteristics
  E.5 Ultra DMA timing and protocol
      E.5.1 Ultra DMA timing assumptions
      E.5.2 Ultra DMA timing parameters
      E.5.3 Ultra DMA Protocol Considerations
  E.6 Cable detection
      E.6.1 80-conductor cable assembly electrical feature
      E.6.2 Host determination of cable assembly type
      E.6.3 Device determination of cable assembly type
F Register Selection Address Summary
G Sample Code for CRC and Scrambling
H FIS Type Field Value Selection
I Physical Layer Implementation Examples
J Command Processing Example
Tables
Figures