ANSI INCITS 417 : 2006

Foreword
Introduction
1 Scope
2 Normative references
   2.1 Normative references
   2.2 Approved references
   2.3 References under development
   2.4 Other references
3 Definitions, symbols, abbreviations, keywords, and conventions
   3.1 Definitions
   3.2 Symbols and abbreviations
   3.3 Keywords
   3.4 Editorial conventions
   3.5 Class diagram and object diagram conventions
   3.6 State machine conventions
   3.7 Bit and byte ordering
   3.8 Notation for procedures and functions
4 General
   4.1 Architecture
   4.2 Names and identifiers
   4.3 State machines
   4.4 Resets
   4.5 I_T nexus loss
   4.6 Expander device model
   4.7 Discover process
   4.8 Phy test functions
5 Physical layer
   5.1 Physical layer overview
   5.2 Passive interconnect
   5.3 Transmitter and receiver device electrical characteristics
   5.4 READY LED signal electrical characteristics
6 Phy layer
   6.1 Phy layer overview
   6.2 8b10b coding
   6.3 Character encoding and decoding
   6.4 Dwords, primitives, data dwords, and invalid dwords
   6.5 Bit order
   6.6 Out of band (OOB) signals
   6.7 Phy reset sequences
   6.8 SP (phy layer) state machine
   6.9 SP_DWS (phy layer dword synchronization) state machine
   6.10 Spin-up
7 Link layer
   7.1 Link layer overview
   7.2 Primitives
   7.3 Clock skew management
   7.4 Idle physical links
   7.5 CRC
   7.6 Scrambling
   7.7 Bit order of CRC and scrambler
   7.8 Address frames
   7.9 Identification and hard reset sequence
   7.10 Power management
   7.11 SAS domain changes
   7.12 Connections
   7.13 Rate matching
   7.14 SL (link layer for SAS phys) state machines
   7.15 XL (link layer for expander phys) state machine
   7.16 SSP link layer
   7.17 STP link layer
   7.18 SMP link layer
8 Port layer
   8.1 Port layer overview
   8.2 PL (port layer) state machines
9 Transport layer
   9.1 Transport layer overview
   9.2 SSP transport layer
   9.3 STP transport layer
   9.4 SMP transport layer
10 Application layer
   10.1 Application layer overview
   10.2 SCSI application layer
   10.3 ATA application layer
   10.4 Management application layer
Annexes
A Jitter tolerance patterns
      A.1 Jitter tolerance pattern (JTPAT)
      A.2 Compliant jitter tolerance pattern (CJTPAT)
B Signal performance measurements
      B.1 Signal performance measurements overview
      B.2 Simple physical link
      B.3 Measurement architecture requirements
      B.4 De-embedding connectors in test fixtures
      B.5 Measurement conditions for signal output at the
          transmitter device
      B.6 Measurement conditions for signal tolerance
      B.7 Measurement conditions for signal output at the
          receiver device
      B.8 Measurement conditions for signal tolerance
          at the receiver device
      B.9 S-parameter measurements
C SAS to SAS phy reset sequence examples
D CRC
      D.1 CRC generator and checker implementation examples
      D.2 CRC implementation in C
      D.3 CRC implementation with XORs
      D.4 CRC examples
E SAS address hashing
      E.1 SAS address hashing overview
      E.2 Hash collision probability
      E.3 Hash generation
      E.4 Hash implementation in C
      E.5 Hash implementation with XORs
      E.6 Hash examples
F Scrambling
      F.1 Scrambler implementation example
      F.2 Scrambler implementation in C
      F.3 Scrambler implementation with XORs
      F.4 Scrambler examples
G ATA architectural notes
      G.1 STP differences from Serial ATA (SATA)
      G.2 STP differences from Serial ATA II
      G.3 Affiliation policies
      G.4 SATA port selector considerations
      G.5 SATA device not transmitting initial Register
          Device-to-Host FIS
H ALIGN and/or NOTIFY insertion rate summary
I Expander device handling of connections
      I.1 Expander device handling of connections overview
      I.2 Connection request - OPEN_ACCEPT
      I.3 Connection request - OPEN_REJECT by end device
      I.4 Connection request - OPEN_REJECT by expander device
      I.5 Connection request - arbitration lost
      I.6 Connection request - backoff and retry
      I.7 Connection request - backoff and reverse path
      I.8 Connection close - single step
      I.9 Connection close - simultaneous
      I.10 BREAK handling during path arbitration
      I.11 BREAK handling during connection
      I.12 STP connection - originated by STP initiator port
      I.13 STP connection - originated by STP target port in
           an STP/SATA bridge
      I.14 STP connection close - originated by STP initiator
           port
      I.15 STP connection close - originated by STP target
           port in an STP/SATA bridge
      I.16 Connection request - XL1:Request_Path to
           XL5:Forward_Open transition
      I.17 Pathway blocked and pathway recovery example
J Primitive encoding
K Messages between state machines
      K.1 Messages between phy layer and other layers
      K.2 Messages between link layer, port layer, and
          management application layer for all protocols
      K.3 Messages between link layer, port layer, and
          transport layer for SSP
      K.4 Messages between link layer, port layer, and
          transport layer for SMP
      K.5 Messages from transport layer to application
          layer for SSP
      K.6 Messages from transport layer to application
          layer for SMP
L Discover process example implementation
      L.1 Discover process example implementation overview
      L.2 Header file
      L.3 Source file
M SAS icon