ARINC 717-15 : 2011

1.0 INTRODUCTION
1.1 Purpose of This Document
1.2 Basic Principles
1.3 System Functions
1.4 Unit Functions
1.5 Reliability and Maintainability
1.6 Interchangeability
1.7 Regulatory Approval
2.0 INTERCHANGEABILITY STANDARDS
2.1 Importance of Interchangeability
2.2 Form Factors and Connectors
2.3 Input and Output Signal Characteristics
2.4 Standard Interwiring
2.5 Power Circuitry
2.6 Weights
2.7 Environmental Specifications
2.8 Abnormal Conditions
3.0 SYSTEM DESIGN
3.1 General
3.2 System Interwiring
3.3 Units
3.4 Data Sources
3.5 Data Multiplexing
3.6 Data Format
3.7 Input Signal Programming
3.8 Input Circuit Protection
3.9 System Accuracy
3.10 Failure Warning and Functional Test
4.0 STANDARD SIGNAL CHARACTERISTICS
4.1 Interface Standards
4.2 Analog Data Inputs
4.3 Digital Data Inputs
4.4 Discrete Data Inputs (On-Off Signals)
4.5 Reference Inputs
4.6 Reference Outputs
4.7 Standard Outputs
4.8 Non-Standard Outputs
5.0 DIGITAL FLIGHT DATA ACQUISITION UNIT DESIGN (DFDAU)
5.1 DFDAU Functions
5.2 DFDAU Inputs
5.3 Output Data Formats
5.4 Optional Digital Port
5.5 Self-Test and Maintainability
5.6 Excitation Output Signals
5.7 Undefined Programmability
6.0 DIGITAL FLIGHT DATA RECORDER DESIGN (DFDR)
6.1 Recording Capacity
6.2 Self Test
6.3 Power Inputs
6.4 Protection
6.5 Data Input
7.0 ACCELEROMETER DESIGN
7.1 Accelerometer Description
7.2 Excitation
7.3 Signal outputs
7.4 Filtering (Output Frequency Response)
7.5 Weight
8.0 FLIGHT DATA ENTRY PANEL DESIGN (FDEP)
8.1 General
8.2 Unassigned DFDAU Interface
8.3 Assigned Interface
8.4 Automatic Means for Entering Documentary Data
9.0 PROVISIONS FOR AUTOMATIC TEST EQUIPMENT
9.1 General
9.2 Unit Identification
ATTACHMENTS
ATTACHMENT 1 - SYSTEM BLOCK DIAAGRAM
ATTACHMENT 2-1 - SYSTEM STANDARD INTERWIRING
ATTACHMENT 2-2 - DFDAU STANDARD INTERWIRING
ATTACHMENT 3-1 - DFDAU CONNECTOR PLACEMENT
ATTACHMENT 3-2 - DFDAU PIN ASSIGNMENT
ATTACHMENT 3-4 - PIN ASSIGNMENT DFDR CONNECTOR
                 DPX2MA-57POOP-34-001
ATTACHMENT 3-5 - ACCELEROMETER FORM FACTOR
ATTACHMENT 3-6 - ACCELEROMETER PIN ASSIGNMENT
ATTACHMENT 3-7 - FDEP PHYSICAL CHARACTERISTICS
ATTACHMENT 3-8 - CONTROL PANEL AND DATA ENTRY PIN
                 ASSIGNMENT
ATTACHMENT 4 - DATA FRAME DESCRIPTION
ATTACHMENT 5-1 - INPUT CONNECTOR PIN ASSIGNMENT
                 STANDARDS
ATTACHMENT 5-2 - SUMMARY OF ANALOG INPUT ASSIGNMENTS
ATTACHMENT 5-3 - SUMMARY OF DISCRETE INPUT ASSIGNMENTS
ATTACHMENT 5-4 - IDENT DISCRETE ASSIGNMENTS
ATTACHMENT 6 - SUMMARY OF ARINC 429 INPUT ASSIGNMENTS
ATTACHMENT 7 - GUIDANCE FOR INPUT ISOLATION
ATTACHMENT 8 - SIGNAL LINE CHARACTERISTICS
ATTACHMENT 9-1 - GENERAL WORD FORMATS AND ENCODING
                 EXAMPLES
ATTACHMENT 9-2 - DIGITAL DATA WAVEFORMS
ATTACHMENT 9-3 - ARINC 429 TIMING TOLERANCES
ATTACHMENT 9-4 - DIGITAL LOGIC LEVELS AND WAVEFORMS
                 (ARINC 717 HARVARD BI-PHASE CODE)
ATTACHMENT 9-5 - "AUXILIARY OUTPUT" SIGNAL LOGIC LEVELS
                 AND WAVEFORMS (ARINC 429 BI-POLAR RZ CODE)
ATTACHMENT 10 - INTERCONNECTIONS FOR FAILURE WARNING
APPENDICES
APPENDIX A - AIDS BACKGROUND
APPENDIX C - DGAS REGULATION ON SECONDARY ATTACHMENTS
ARINC Standard - Errata Report
APIM