Documentation on design automation subjects. Mathematical algorithm hardware description languages for system level modeling and verification (HDLMath)

Available format(s)

Hardcopy , PDF

Language(s)

English

Published date

01-10-2017

Publisher

British Standards Institution

FOREWORD
INTRODUCTION
1 Scope
2 Normative references
3 Terms and definitions
4 Definition and positioning of HDLMath
5 Functional requirements of HDLMath
6 Comparison of current HDLMath languages
7 Conclusion
Bibliography

Specifies the main functional requirements for an HDLMath language and compares existing HDLMath languages from the viewpoint of designers.

A hardware description language provides a means to describe the behavior of a system precisely and concisely. This document describes the main functional requirements for an HDLMath language and compares existing HDLMath languages from the viewpoint of designers. It is intended to accelerate the standardization of a mathematical algorithm design language and to help establish a new and good system modeling and verification environment.

Committee	EPL/501
DocumentType	Standard
Pages	20
PublisherName	British Standards Institution
Status	Current

Standards	Relationship
IEC TR 63051:2017	Identical

IEC 61691-1-1:2011	Behavioural languages - Part 1-1: VHDL Language Reference Manual
IEC 62530:2011	SystemVerilog - Unified Hardware Design, Specification, and Verification Language
IEC TR 62856:2013	Documentation on design automation subjects - The Bird's-eye View of Design Languages (BVDL)

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PD IEC/TR 63051:2017

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Table of Contents

Abstract

Scope

General Product Information

International Equivalents

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