VSB - Parallel Sub-system Bus of the IEC 60821 VMEbus

Available format(s)

Hardcopy , PDF , PDF 3 Users , PDF 5 Users , PDF 9 Users

Language(s)

English - French

Published date

12-30-1988

Publisher

International Electrotechnical Committee

The VSB bus was designed to meet the needs of multiprocessor systems based on high-performance 32-bit microprocessors built up from board assemblies. lt includes a high-speed asynchronous data transfer bus allowing masters to direct the transfer of binary data to and from slaves according to 4 kinds of cycles: address-only, single-transfer, block-transfer and interrupt-acknowledge cycles. It also includes an arbitration bus enabling arbiter modules and/or requester modules to coordinate the use of the data-transfer bus according to two arbitration methods (series or parallel). Note: -For the price of this publication, please consult the ISO/IEC price-code list.

DevelopmentNote	Also numbered as BS 7241(1989) (09/2005)
DocumentType	Standard
Pages	311
PublisherName	International Electrotechnical Committee
Status	Current

Standards	Relationship
DIN IEC 60822:1992-02	Identical
HD 576 : 200S1	Identical
UNE 20822:1993	Identical

BS IEC 821 : 1992 AMD 8349	IEC 821 VMEBUS. MICROPROCESSOR SYSTEM BUS FOR 1 BYTE TO 4 BYTE DATA
EN 60821:1994/corrigendum:1994	IEC 60821 VMEbus - Microprocessor system bus for 1 byte to 4 byte data
CEI EN 60821 : 1996	IEC 821 VMEBUS - MICROPROCESSOR SYSTEM BUS FOR 1 BYTE TO 4 BYTE DATA
BS EN 60821:1995	IEC 821 VMEbus. Microprocessor system bus for 1 byte to 4 byte data
IEC 60821:1991	VMEbus - Microprocessor system bus for 1 byte to 4 byte data