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IEEE 1076.3-1997

Current
Current

The latest, up-to-date edition.

IEEE Standard VHDL Synthesis Packages
Available format(s)

PDF

Language(s)

English

Published date

06-05-1997

1 Overview
 1.1 Scope
 1.2 Terminology
 1.3 Conventions
2 References
3 Definitions
4 Interpretation of the standard logic types
 4.1 The STD_LOGIC_1164 values
 4.2 Static constant values
 4.3 Interpretation of logic values
5 The STD_MATCH function
6 Signal edge detection
7 Standard arithmetic packages
 7.1 Allowable modifications
 7.2 Compatibility with IEEE Std 1076-1987
 7.3 The package texts
Annex A (informative) Notes on the package functions
      A.1 General considerations
      A.2 Arithmetic operator functions
      A.3 Relational operator functions
      A.4 Shift functions
      A.5 Type conversion functions
      A.6 Logical operator functions
      A.7 The STD_MATCH function

This standard defines standard practices for synthesizing binary digital electronic circuits from VHDL source code.

Committee
Design Automation
DevelopmentNote
Includes a 3.5" DOS disc. (01/2000)
DocumentType
Standard
ISBN
978-0-7381-0989-3
Pages
49
PublisherName
Institute of Electrical & Electronics Engineers
Status
Current
Supersedes

IEEE 1076-2008 REDLINE IEEE Standard VHDL Language Reference Manual
BS IEC 61691-1-1:2011 Behavioural languages VHDL Language reference manual
IEC 61691-1-1:2011 Behavioural languages - Part 1-1: VHDL Language Reference Manual
IEEE DRAFT 1076.6 : D1.12A 99 DRAFT STANDARD FOR VHDL REGISTER TRANSFER LEVEL SYNTHESIS
ANSI INCITS TR 44 : 2008 INFORMATION TECHNOLOGY - FIBRE CHANNEL SIGNAL MODELING-2 (FCSM-2)
BS IEC 62050:2005 VHDL register transfer level (RTL) synthesis
IEC 62050:2005 VHDL Register Transfer Level (RTL) synthesis
ANSI INCITS TR 44 : 2008(R2018) INFORMATION TECHNOLOGY - FIBRE CHANNEL SIGNAL MODELING-2 (FCSM-2)
PD R217-020:2002 Electronic system specification languages. VHDL modelling guidelines
IEEE 1076.6-2004 IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis
IEEE 1076.6-1999 IEEE Standard for VHDL Register Transfer Level Synthesis

IEEE 1164-1993 IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164)
IEEE 1076-2008 REDLINE IEEE Standard VHDL Language Reference Manual
IEEE 1076-1993 IEEE Standard VHDL Language Reference Manual

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