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IEEE 1076.6-2004

Withdrawn
Withdrawn

A Withdrawn Standard is one, which is removed from sale, and its unique number can no longer be used. The Standard can be withdrawn and not replaced, or it can be withdrawn and replaced by a Standard with a different number.

IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis
Available format(s)

PDF

Withdrawn date

01-09-2010

Language(s)

English

Published date

10-11-2004

Publisher

Institute of Electrical & Electronics Engineers

FOREWORD
IEEE Introduction
1. Overview
   1.1 Scope
   1.2 Compliance to this standard
   1.3 Terminology
   1.4 Conventions
2. References
3. Definitions and acronyms
   3.1 Definitions
   3.2 Acronyms
4. Predefined types
5. Verification methodology
   5.1 Combinational verification
   5.2 Sequential verification
6. Modeling hardware elements
   6.1 Edge-sensitive sequential logic
   6.2 Level-sensitive sequential logic
   6.3 Three-state logic and busses
   6.4 Combinational logic
   6.5 ROM and RAM memories
7. Pragmas
   7.1 Attributes
   7.2 Metacomments
8. Syntax
   8.1 Design entities and configurations
   8.2 Subprograms and packages
   8.3 Types
   8.4 Declarations
   8.5 Specifications
   8.6 Names
   8.7 Expressions
   8.8 Sequential statements
   8.9 Concurrent statements
   8.10 Scope and visibility
   8.11 Design units and their analysis
   8.12 Elaboration
   8.13 Lexical elements
   8.14 Predefined language environment
Annex A (informative) - Syntax summary
Annex B (normative) - Synthesis package RTL_ATTRIBUTES
Annex C (informative) - List of Participants
Index

Describes a subset of very high-speed integrated circuit hardware description language (VHDL) that ensures portability of VHDL descriptions between register transfer level synthesis tools. Defines how the semantics of VHDL shall be used, for example, to model level-sensitive and edge-sensitive logic. Also describes the syntax of the language with reference to what shall be supported and what shall not be supported for interoperability.

Committee
Design Automation
DevelopmentNote
Supersedes IEEE DRAFT 1076.6. (10/2004) Also numbered as IEC 62050 (07/2005)
DocumentType
Standard
Pages
118
PublisherName
Institute of Electrical & Electronics Engineers
Status
Withdrawn
Supersedes

IEEE 1076-2008 REDLINE IEEE Standard VHDL Language Reference Manual
IEC 62531:2012 Property Specification Language (PSL)
BS IEC 61691-1-1:2011 Behavioural languages VHDL Language reference manual
IEC 61691-1-1:2011 Behavioural languages - Part 1-1: VHDL Language Reference Manual
BS ISO 10110-19:2015 Optics and photonics. Preparation of drawings for optical elements and systems General description of surfaces and components
ISO 10110-19:2015 Optics and photonics Preparation of drawings for optical elements and systems Part 19: General description of surfaces and components
BS IEC 62531:2012 IEEE standard for property specification language (PSL)
DIN ISO 10110-19 E : 2016 OPTICS AND PHOTONICS - PREPARATION OF DRAWINGS FOR OPTICAL ELEMENTS AND SYSTEMS - PART 19: GENERAL DESCRIPTION OF SURFACES AND COMPONENTS (ISO 10110-19:2015)
DIN ISO 10110-19:2016-04 OPTICS AND PHOTONICS - PREPARATION OF DRAWINGS FOR OPTICAL ELEMENTS AND SYSTEMS - PART 19: GENERAL DESCRIPTION OF SURFACES AND COMPONENTS (ISO 10110-19:2015)
13/30253349 DC : 0 BS ISO 10110-19 - OPTICS AND PHOTONICS - PREPARATION OF DRAWINGS FOR OPTICAL ELEMENTS AND SYSTEMS - PART 19: OPTICAL FREEFORM SURFACES
IEEE 1850-2010 IEEE Standard for Property Specification Language (PSL)

IEEE 1164-1993 IEEE Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164)
IEEE 1076.3-1997 IEEE Standard VHDL Synthesis Packages
IEEE/IEC 61691-1-1-2004 IEC 61691-1-1 Ed.1 (IEEE Std 1076(TM)-2002): Behavioural Languages - Part 1-1: VHDL Language Reference Manual
IEEE 1076-2008 REDLINE IEEE Standard VHDL Language Reference Manual

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