SN EN 60821 : 1994
Current
The latest, up-to-date edition.
Describes a high performance backplane bus for use in microprocessor bases systems. This parallel bus supports single and block transfer cycles on a 32-bit non-multiplexed address and data highway. Transmission is governed by an asynchronous handshaken protocol. The bus allocation provides for multiprocessor architectures. This bus also supports inter-module interrupts for facilitating quick response to internal and external events. The mechanics of the boards and chasses are based on IEC 297. Note- This bus is similar to the VME bus.
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