IEC 60935:1996

FOREWORD
Section 0 Normative References
Section 1 Object, scope and introductory overview
1.1 Object and scope
1.2 Introductory overview
     1.2.1 FASTBUS Operations
     1.2.2 Segment Interconnects
     1.2.3 Control and Status Registers
     1.2.4 Geographical Addressing
     1.2.5 Block and Pipelined Transfers
     1.2.6 Address Locked and Arbitration Locked
            Operations
     1.2.7 Sparse Data Scan
     1.2.8 BROADCAST Operations
     1.2.9 Arbitration for Bus Mastership
     1.2.10 Interrupts
     1.2.11 Timing
     1.2.12 Initialization
     1.2.13 Diagnostic Tools
Section 2 Conventions, definitions, abbreviations and
          symbols
2.1 Interpretation of this standard
2.2 Notations and logic signal conventions
2.3 Definitions (according to English alphabetical order)
2.4 Acronyms
2:5 Symbols
Section 3 Signals, signal lines and pins
3.1 Types of signal lines
3.2 Signal nomenclature
3.3 Brief description of signals, lines and pins
     3.3.1 AS - Address Sync (T, Master)
     3.3.2 AK - Address Acknowledge (T, Slave or ANC)
     3.3.3 EG - Enable Geographical (C, Master or ANC)
     3.3.4 MS - Mode Select (C, Master)
     3.3.5 AD - Address/Data (1, Master or Slave)
     3.3.6 SS - Slave Status (I, Slave)
     3.3.7 DS - Data Sync (T, Master)
     3.3.8 DK - Data Acknowledge (T, Slave or ANC)
     3.3.9 RD - Read (C, Master)
     3.3.10 PE - Parity Enable (I, Master or Slave)
     3.3.11 PA - Parity (I, Master or Slave)
     3.3.12 WT - Wait (A, Any Device)
     3.3.13 AR - Arbitration Request (A, Master)
     3.3.14 AG - Arbitration Grant (TA, ANC)
     3.3.15 AL - Arbitration Level (IA, Master)
     3.3.16 GK - Grant Acknowledge (TA, Master)
     3.3.17 AI - Arbitration Request Inhibit (CA, ANC)
     3.3.18 SR - Service Request (A, Master or Slave)
     3.3.19 RB - Reset Bus (A, Master or Master via SIs)
     3.3.20 BH - Bus Halted (C, ANC)
     3.3.21 GA - Geographical Address (F, Hardwired)
     3.3.22 TP - T Pins (I, Slave)
     3.3.23 DL, DR - Daisy Chain (I, Master or Slave)
     3.3.24 TX, RX - Serial Network Lines (A, Master or
            Slave)
     3.3.25 TR - Terminated Restricted Use Lines
     3.3.26 UR - Un-terminated Restricted Use Lines
     3.3.27 Other Lines and Pins
3.4 Bus loading
     3.4.1 Voltage and Current Limits For Signal Lines
            and F Pins
Section 4 FASTBUS Operations: Addressing
4.1 Logical Addressing
4.2 Geographical Addressing
4.3 Broadcast Addressing
     4.3.1 Master's Control of a Broadcast
     4.3.2 Slave Response to Broadcast Operations
4.4 Secondary Addressing
4.5 Sparse Data Scan and Pattern Select Operation
Section 5 FASTBUS Operations: Timing, Sequences and
          Responses
5.1 General Master/Slave Timing Requirements
     5.1.1 Master Signal Timing Requirements
     5.1.2 Slave Signal Timing Requirements
     5.1.3 Use of Wait (WT)
5.2 Primary Address Cycles
     5.2.1 Master Sequence for Asserting AS
     5.2.2 Slave Response to AS(u)
     5.2.3 Master Response to AK(u)
5.3 Operations
     5.3.1 Master Sequence for Asserting DS
     5.3.2 Slave Response to DS(t)
     5.3.3 Discussion of Slave Status Responses
     5.3.4 Master Response to DK(t)
5.4 Master Reset Bus (RB)
     5.4.1 Master Assertion of RB
     5.4.2 Device Response to RB
5.5 Device Response to Power On
5.6 State Diagrams for FASTBUS Operations
Section 6 Bus Arbitration
6.1 Bus Line Usage for the Arbitration Process
6.2 The Arbitration Process
6.3 Arbitration Rules
     6.3.1 Master Assertion of AR and Segment
            Interconnect Passing of AR
     6.3.2 ATC Assertion and Release of AI
     6.3.3 ATC Assertion and Release of AG
     6.3.4 Master Assertion and Release of AL
     6.3.5 Master Assertion and Release of GK
6.4 System Wide Arbitration
Section 7 Ancillary Logic on a Segment
7.1 Arbitration Timing Control (ATC)
     7.1.1 ATC Generation of AI
     7.1.2 ATC Generation of AG
7.2 Geographical Address Control
7.3 System Handshake Generation (Broadcast)
7.4 Run/Halt Control and Bus Halted
7.5 Terminators
7.6 Ancillary Logic for Crate Segments
7.7 Ancillary Logic for Cable Segments
Section 8 Control and Status Register Space
8.1 Selective Set and Clear Functions
8.2 Normal CSR Space Allocation
8.3 CSR Register
     8.3.1 Device IDs and their Allocation
     8.3.2 Control and Status Bit Allocation
8.4 CSR Register
8.5 CSR Register
8.6 CSR Register
8.7 CSR Register
8.8 CSR Register
8.9 CSR Register
8.10 CSR Register
8.11 CSR Register
8.12 CSR Register 9 AND CSR Register 1Ch to 1Fh
8.13 CSR Registers Ah to Fh
8.14 CSR Registers 20h to 3Fh
8.15 CSR Registers 70h to 81h
8.16 CSR Registers A0h to AFh, B0h to BFh and C0h to CFh
8.17 CSR Registers 8000 0000h to BFFF FFFFh, Parameter Space
8.18 Clearing of CSR Bits
8.19 CSR register
8.20 CSR Register
Section 9 Interrupts
9.1 Interrupt Operation
9.2 The Service Request Line
9.3 SR line Saturation
Section 10 Interconnection of Segments
10.1 Types of Segment Interconnects
10.2 Operation Passing
10.3 Contention Resolution
10.4 Route Tables
10.5 Control and Status Registers
     10.5.1 CSR#0 - ID, Status and Control
     10.5.2 CSR#1 Far-side Arbitration Level
     10.5.3 CSR#8 Near-side Arbitration Level
     10.5.4 CSR#9 Timer Control Register
     10.5.5 CSR#40h Route Table Address Register
     10.5.6 CSR#41h Route Table Data Register
     10.5.7 CSR#42h Near-side Geographical Address
     10.5.8 CSR#43h Far-side Geographical Address
     10.5.9 Effect of Various Actions on CSR Bits in SIs
10.6 Route Tables
     10.6.1 Pass, Destination and Base Information
     10.6.2 Generation Rules
10.7 SI Actions
     10.7.1 Address Recognition
     10.7.2 SI Arbitration
     10.7.3 Contention Resolution
     10.7.4 Negative Responses
     10.7.5 Modification of Geographical and Broadcast
            Addresses
     10.7.6 Operation Passing
     10.7.7 SI use and Generation of Parity
     10.7.8 Segment Interconnect Response to RB
     10.7.9 Timing Requirements
10.8 Base Address Register
Section 11 Block and Pipelined Transfers
11.1 Block and Pipelined Transfer Termination
11.2 Block Transfer Internal Address Incrementation
11.3 FIFOs and Errors in Data Transfer
11.4 Multimodule Data Transfers
Section 12 Signal Characteristics
12.1 Signal Levels
Section 13 Modules
13.1 Module Circuit Board
     13.1.1 Grounding Area for Static Charge Discharge
     13.1.2 Stiffener Bars
13.2 Connectors
     13.2.1 Segment Connector
     13.2.2 Module Auxiliary Connector
     13.2.3 Other Connectors
     13.2.4 Segment and Auxiliary Connector Contact
            Designations
13.3 Temperature Considerations and Power Dissipation
     13.3.1 Die and Module Temperatures
     13.3.2 Power Dissipation
     13.3.3 Cooling
13.4 Front Panel
13.5 Module Activity Indicators
13.6 Labeling of Power Requirements
13.7 Transients
Section 14 Crates
14.1 Crate Construction
14.2 Crate Backplane
     14.2.1 Crate Segment Connector and Associated Wiring
     14.2.2 Crate Auxiliary Connector
     14.2.3 Connector Guides
     14.2.4 Back-plane Current Requirements
     14.2.5 Other Back-plane Items
14.3 Cooling
14.4 Run/halt Switch Assembly
14.5 Circuit Boards mounted at rear of Back-plane
14.6 Crate Markings
14.7 Contacts for Static Charge discharge
Section 15 Power
Section 16 Cable Segment
16.1 Signals on a Cable Segment
16.2 Cable Segment Connectors and Contact Assignments
Annexes
Figures
Tables