TR NWT 000393 : ISSUE 2

1 Introduction
1.1 Purpose
1.2 Changes from Issue 1 of TR-TSY-000393
1.3 Document Organization
1.4 Requirements Definition and Conventions
2 DSL Overview and Related Technical References
2.1 Description of DSL Technology
2.2 DSL Transmission and System Interfaces
2.3 Transport Systems Embedding DSLs
3 Loop Plant Environment
4 Spectrum Management
4.1 Crosstalk
4.2 Electromagnetic Emission and Immunity
                 Requirements and Objectives
5 Transmission Characteristics
5.1 Transmission Method
5.2 Line Code
5.2.1 Characteristics of Pulses
5.2.2 Power Spectrum of the Transmitted Signal
5.3 Baud Rate
5.4 Timing
5.5 Jitter
5.5.1 NT Input Signal Jitter Tolerance
5.5.2 NT Output Jitter Limitation
5.5.3 LT Input Signal Jitter Tolerance
5.5.4 LT Output Jitter Limitation
5.6 Message Propagation Delay
5.7 Frame Structure
5.7.1 Synchronization Word
5.7.2 User Data (2B+D)
5.7.3 M Channel
5.7.4 Superframes
5.7.5 Frame Offset
5.8 Scrambling Method
5.9 Transmitter Linearity
5.10 Start-Up Procedure
5.10.1 Definition
5.10.2 Continuous Operation
5.10.3 RESET
5.10.4 Timers
5.10.5 Signals During Start-Up
5.10.6 Line Rate During Start-Up
5.10.7 Start-Up Sequence
5.11 NT Maintenance Modes
5.11.1 NT Quiet Mode
5.11.2 Insertion Loss Measurement Test
5.11.3 NT Quiet Mode and Insertion Loss Measurement
                 Test Trigger Signal
5.11.4 dc Signaling Format
5.11.5 Low Frequency ac Signaling Format
6 Generic DSL Power and Interface Requirements
6.1 Power Requirements
6.2 Line Interface
6.2.1 Impedance and Return Loss
6.2.2 Sealing Current
6.2.3 Metallic Termination
6.2.4 Behavior of the NT during Metallic Testing
6.2.5 NT Network Side Resistance to Ground
6.2.6 Longitudinal Output Voltage
6.2.7 NT Longitudinal Balance
6.2.8 LT Longitudinal Balance
6.2.9 Electrical Protection
6.2.10 Electrostatic Discharge
6.2.11 Electrical Safety
REFERENCES
APPENDIX A: GLOSSARY
APPENDIX B: CHARACTERISTICS OF TELEPHONE LOOP PLANT
APPENDIX C: LABORATORY MEASUREMENT OF BER
APPENDIX D: SUBSCRIBER LOOPS FOR TESTING BER
LIST OF FIGURES
Figure 2-1 Access Reference Configuration
Figure 2-2 Architectures for ISDN Basic Access
Figure 4-1 Models of 1% NEXT for 18Kft of 22GA PIC
Figure 5-1 2B1Q Encoding of 2B+D Bit Fields
Figure 5-2 Normalized Pulse from NT or LT Transmitter
Figure 5-3 Upper Bound of Power Density of Signal from
                 NT or LT Transmitter
Figure 5-4 Range of Permissible Sinusoidal Jitter
                 Signal Originating from LT
Figure 5-5 ISDN Basic Access 2B1Q DSL 1.5 Milisecond
                 Basic Frame
Figure 5-6a LT-to-NT 2B1Q Superframe Technique &
                 Overhead Bit Assignments
Figure 5-6b NT-to-LT 2B1Q Superframe Technique &
                 Overhead Bit Assignments
Figure 5-7 CRC-12 Generator
Figure 5-8 DSL Framing and Overhead Function Temporal
                 Relationship
Figure 5-9 Scrambler and Descrambler
Figure 5-10 Measurement of DSL Transmitter Linearity
Figure 5-11 Definitions of Signals During Start-Up
Figure 5-12 State Sequence for DSL Transceiver Start-Up
Figure 5-13 NT Loop Testing States
Figure 6-1 Minimum Return Loss
Figure 6-2 Illustration of dc Characteristics of the NT
Figure 6-3 Measurement Method for Longitudinal Output
                 Voltage
Figure 6-4 NT-Longitudinal Balance
Figure 6-5 Measurement Method for Longitudinal Balance
Figure 6-6 LT-Longitudinal Balance
Figure B-1 1983 Loop Survey
Figure B-2 1983 Loop Survey - Non-Loaded Loops
Figure B-3 1983 Loop Survey - Loop Loss Distribution Curves
Figure C-1 Laboratory Test Set-Up for Measuring BER
Figure C-2 PSD for Simulated NEXT for Testing 2B1Q System
Figure C-3 Crosstalk Calibration Impedance, Zc
Figure C-4 Waveform for Longitudinal Noise
Figure C-5 PSD of Assumed Interferers
Figure D-1a Loops for Testing Received Signal
                 Performance No. 1 - No. 5
Figure D-1b Loops for Testing Received Signal
                 Performance No. 6 - No. 10
Figure D-1c Loops for Testing Received Signal
                 Performance No. 11 - No. 15