ANSI INCITS 397 VOL-3 : 2005
Superseded
A superseded Standard is one, which is fully replaced by another Standard, which is a new edition of the same Standard.
A superseded Standard is one, which is fully replaced by another Standard, which is a new edition of the same Standard.
INFORMATION TECHNOLOGY - AT ATTACHMENT WITH PACKET INTERFACE - 7 VOLUME 3 - SERIAL TRANSPORT PROTOCOLS AND PHYSICAL INTERCONNECT (ATA/ATAPI-7 V3)
Hardcopy , PDF
18-04-2024
English
01-01-2005
Foreword
Introduction
1 Scope
2 Normative references
2.1 Approved references
2.2 References under development
2.3 Other references
3 Definitions, abbreviations, and conventions
3.1 Definitions and abbreviations
3.2 Conventions
4 General operational requirements
5 I/O register descriptions
6 Command descriptions
7 Parallel interface physical and electrical requirements
8 Parallel interface signal assignments and descriptions
9 Parallel interface general operating requirements
of the physical, data link, and transport layers
10 Parallel interface register addressing
11 Parallel interface transport Protocols
12 Parallel interface timing
13 Serial interface general overview
13.1 Overview
13.2 Sub-module operation
13.3 Parallel ATA Emulation (Optional)
14 Serial interface physical layer
14.1 Overview
14.2 Connectors specifications
14.3 Cable assemblies
14.4 Phy (Physical layer electronics)
14.5 Electrical features
14.6 Elasticity buffer management
14.7 BIST (Built in self test)
15 Serial interface Link layer
15.1 Overview
15.2 Encoding method
15.3 Transmission Method
15.4 Primitives
15.5 CRC calculation
15.6 Scrambling
15.7 Link layer state diagrams
16 Serial interface Transport layer
16.1 Transport layer overview
16.2 Frame Information Structure (FIS)
16.3 Overview
16.4 Payload content
16.5 FIS types
16.6 Host transport states
16.7 Device transport states
17 Serial interface Device Command Layer Protocol
17.1 COMRESET or SRST sent by Host
17.2 Power-on and COMRESET protocol diagram
17.3 Device Idle protocol
17.4 Software reset protocol
17.5 EXECUTE DEVICE DIAGNOSTIC command protocol
17.6 DEVICE RESET command protocol
17.7 Non-data command protocol
17.8 PIO data-in command protocol
17.9 PIO data-out command protocol
17.10 DMA data-in command protocol
17.11 DMA data out command protocol
17.12 PACKET protocol
17.13 READ DMA QUEUED command protocol
17.14 WRITE DMA QUEUED command protocol
18 Host command layer state diagram
18.1 Overview
18.2 Device Emulation of nIEN with Interrupt Pending
(Informative)
19 Serial interface host adapter register interface
19.1 Overview
19.2 SStatus, SError and SControl registers
20 Serial interface error handling
20.1 Architecture
20.2 Phy error handling overview
20.3 Link error handling overview
20.4 Transport error handling
Annexes
A Bibliography
B Command Set Summary
C Design and Programming Considerations for
Large Physical Sector Sizes
D Device Determination of Cable Type
E Signal Integrity and UDMA Guide
F Register Selection Address Summary
G Sample Code for Serial CRC Scrambling
G.1 CRC calculation
G.2 Scrambling calculation
G.3 Example frame
H FIS Type Field Value Selection
H.1 Overview
H.2 Type field values
I Physical Layer Implementation Examples
I.1 Cable construction example
I.2 Contact material and plating
I.3 Relationship of frequency to the jitter
specification
I.4 Sampling BER and jitter formulas
I.5 DC and AC coupled transmitter examples
I.6 OOB signal and squelch detector examples
J Command Processing Example
J.1 Non-data commands
Tables
Figures
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