IEC 62530-2:2023
Current
The latest, up-to-date edition.
SystemVerilog - Part 2: Universal Verification Methodology Language Reference Manual
Hardcopy , PDF , PDF 3 Users , PDF 5 Users , PDF 9 Users
English
11-10-2023
IEC 62530-2:2023 establishes the Universal Verification Methodology (UVM), a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800™.1. This is an IEC/IEEE dual logo standard.
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