JEDEC JESD78F:2022

Name: JEDEC JESD78F:2022
Brand: JEDEC

Superseded

View Superseded by

IC Latch-Up Test

Available format(s)

Hardcopy , PDF

Superseded date

20-01-2023

Language(s)

English

Published date

01-01-2022

Publisher

JEDEC Solid State Technology Association

This standard establishes the procedure for testing, evaluation and classification of devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined latch-up stress.

DocumentType	Revision
Pages	86
PublisherName	JEDEC Solid State Technology Association
Status	Superseded
SupersededBy	JEDEC JESD78F.01:2022
Supersedes	JEDEC JESD 78E:2016

DSCC 22210:2023	MICROCIRCUIT, MEMORY, DIGITAL, CMOS, LOW POWER REPROGRAMMABLE 481,000 LOGIC ELEMENT FLASH FIELD PROGRAMMABLE GATE ARRAY WITH DECOUPLING CAPACITORS, FLIP CHIP Pb FREE BUMP, MONOLITHIC SILICON
DSCC 06233D:2023	MICROCIRCUIT, DIGITAL, RADIATION HARDENED, LOW VOLTAGE CMOS, MINIMUM SKEW ONE-TO-EIGHT CLOCK DRIVER, LVTTL COMPATIBLE INPUTS AND OUTPUTS, MONOLITHIC SILICON
DSCC 89764D:2023	MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 4K X 8 DUAL PORT STATIC RANDOM ACCESS MEMORY, MONOLITHIC SILICON
DSCC 01517G:2022	MICROCIRCUIT, MEMORY, DIGITAL, CMOS, RADIATION-HARDENED, 3.3 V, 32K X 8-BIT PROM, MONOLITHIC SILICON
DSCC 07239B:2023	MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 512K x 16-BIT (8M), STATIC RANDOM ACCESS MEMORY (SRAM), (3.3 V), MONOLITHIC SILICON
DSCC 07235B:2023	MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 128K x 16-BIT (2M), STATIC RANDOM ACCESS MEMORY (SRAM), (3.3 V), MONOLITHIC SILICON
DSCC07241B:2024	MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 1M x 4-BIT (4M), STATIC RANDOM ACCESS MEMORY (SRAM), (3.3 V), MONOLITHIC SILICON