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R217-021 : 2001

Current

Current

The latest, up-to-date edition.

ELECTRONIC SYSTEM SPECIFICATION LANGUAGES - STANDARD METHOD FOR BUILDING VHDL MODELS OF COMPONENT LIBRARIES

Published date

12-01-2013

1 General principles
  1.1 Introduction
  1.2 Recommended reading
  1.3 File management
2 Code layout
  2.1 Naming
  2.2 Commenting
  2.3 Film layout
  2.4 Statement layout
3 Language usage
  3.1 General usage
      3.1.1 Data types
      3.1.2 Packages
      3.1.3 Configurations
      3.1.4 Constants
      3.1.5 Assertions
      3.1.6 Qualified expressions and type conversion
      3.1.7 Interface lists
      3.1.8 Wait statements
      3.1.9 Loops
  3.2 Behavioral usage
      3.2.1 General aspects of a behavioral model
      3.2.2 Data types
      3.2.3 Logic data types
      3.2.4 Naming conventions
      3.2.5 Event and signal handling
      3.2.6 Subprograms
      3.2.7 Variables
      3.2.8 Deferred constants
      3.2.9 Component binding
      3.2.10 Initialization and default values
      3.2.11 Miscellaneous
  3.3 RTL usage
      3.3.1 General aspects of the RTL model
      3.3.2 Data types
      3.3.3 VHDL objects and structural elements
      3.3.4 Process structures
      3.3.5 Subprograms
      3.3.6 Architecture structures
      3.3.7 Configurations
      3.3.8 Loops
      3.3.9 Naming conventions
Annex A: Standard packages
Annex B: References

Provides rules and guidelines for hand-coded VHDL models, with the definitions.

Committee
TC 217
DocumentType
Standard
PublisherName
European Committee for Standards - Electrical
Status
Current

Standards Relationship
PD R217-021:2002 Identical

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