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TR NWT 000357 : ISSUE 2

Superseded

Superseded

A superseded Standard is one, which is fully replaced by another Standard, which is a new edition of the same Standard.

GENERIC REQUIREMENTS FOR ASSURING THE RELIABILITY OF COMPONENTS USED IN TELECOMMUNICATIONS EQUIPMENT

Superseded date

03-01-2001

Published date

01-12-2013

1 INTRODUCTION
1.1 General
1.2 Background
1.3 Organization of Document
1.4 Appropriate Applications
1.5 Changes from Previous Issue
1.6 Requirements Specific to GaAs Technology
1.7 Generic Component Requirements Documents
1.8 Requirements Terminology
2 ENSURING COMPONENT RELIABILITY - GENERAL
              INFORMATION
2.1 Quality Versus Reliability
2.2 Component and Component Manufacturer
              Qualification Programs
2.3 Lot-to-Lot Quality and Reliability Control
2.4 Feedback and Corrective Action Programs
2.5 ESD Damage
2.6 Device Manufacturer's Monitor Programs
2.7 Summary
3 DEVICE QUALITY LEVELS
3.1 Normal System Requirements
3.2 Exceptions
3.3 Quality Level Determination
4 COMPONENT AND COMPONENT MANUFACTURER
              QUALIFICATION PRACTICES
4.1 Controls on Component Use
4.2 Component Manufacturer Qualification Procedures
4.3 Component Qualification Practices
4.4 Required Qualification Tests, Sequences, and
              Sample Plans
4.5 Acceptable Alternative Part Qualification
              Practices
4.6 Qualification Testing for GaAs Devices
5 LOT-TO-LOT QUALITY AND RELIABILITY CONTROL
5.1 Lot Acceptance Testing Considerations
5.2 Quality and Reliability Audits
5.3 Treatment of Failed Lots
5.4 Summary of Vendor History Data
5.5 Additional Considerations
5.6 Required Lot Acceptance Tests for Different
              Device Types
5.7 Acceptable Alternative Lot-to-Lot Control Practices
5.8 Lot Acceptance Tests For GaAs Devices
6 FEEDBACK AND CORRECTIVE ACTION PROGRAMS
6.1 Need for Feedback and Corrective Action Programs
6.2 Sources of Data
6.3 Data Summary and Analysis
7 COMPONENT STORAGE AND HANDLING
7.1 Flow of Materials
7.2 Material Review System
7.3 Stockroom Inventory Practices
7.4 Handling of ESD-Sensitive Components
8 DOCUMENTATION, TEST DATA, AND OTHER COMPONENT
              INFORMATION
8.1 Summaries of Relevant Documentation and
              Management Reports
8.2 Availability of, and Access to, Relevant
              Information
9 SPECIAL TEST METHODS/CRITERIA
9.1 Temperature-Humidity-Bias Testing
9.2 Flammability Testing
9.3 ESD Threshold
10 MODEL COMPONENT RELIABILITY ASSURANCE CHECKLIST
11 REFERENCES
11.1 Referenced Bellcore Documents
11.2 Referenced Military Documents
11.3 Other Referenced Documents
11.4 GaAs Related Documents
11.5 Other Related Documents
12 GLOSSARY
12.1 Symbols, Acronyms, and Units
12.2 Terms
Appendix A: Lot Tolerance Percent Defective Tables
Appendix B: Acceptable Quality Level Tables
Appendix C: Relationship Between Various Tests and Test
              Schedules
Appendix D: Example of Comprehensive Component Engineering
              Program Items and Interfaces
LIST OF FIGURES
Figure 2-1 Essential Elements of a Component Reliability
              Assurance Program
Figure 4-1 Development of Purchase Specifications
Figure 4-2 The two major types of GaAs FETs:
              a) MESFET
              b) JFET
Figure 4-3 Cross-section of a GaAs Monolithic
              Microwave IC (MMIC)
Figure 9-1 Schematic of Human Body Model ESD Simulator
LIST OF TABLES
Table 3-1 Definition of Quality Levels
Table 4-1 Qualification Tests for Hermetic (Si)
              Integrated Circuits
Table 4-2 Qualification Tests for Non-Hermetic (Si)
              Integrated Circuits
Table 4-3 Qualification Tests for Hermetic Discrete (Si)
              Semiconductors
Table 4-4 Qualification Tests for Non-Hermetic Discrete
              (Si) Semiconductors
Table 4-5 Qualification Tests for Capacitors
Table 4-6 Qualification Tests for Resistors
Table 4-7 Qualification Tests for Inductive Devices
Table 4-8 Qualification Tests for Electromechanical Relays
Table 4-9 Qualification Tests for ``Other Devices'
Table 4-10 Alternative IEC Test Methods
Table 4-11 Comparison of GaAs and Silicon Properties
Table 4-12 Qualification Tests for Hermetic (GaAs)
              Integrated Circuits
Table 4-13 Qualification Tests for Non-Hermetic (GaAs)
              Integrated Circuits
Table 4-14 Qualification Tests for Hermetic Discrete
              (GaAs) Semiconductors
Table 4-15 Qualification Tests for Non-Hermetic Discrete
              (GaAs) Semiconductors
Table 5-1 Lot Acceptance Tests for (Si) Integrated Circuits
Table 5-2 Lot Acceptance Tests for Discrete (Si)
              Semiconductors
Table 5-3 Lot Acceptance Tests for Capacitors
Table 5-4 Lot Acceptance Tests for Resistors
Table 5-5 Lot Acceptance Tests for Inductive Devices
Table 5-6 Lot Acceptance Tests for Electromechanical Relays
Table 5-7 Lot Acceptance Tests for ``Other Components'
Table 5-8 Alternative IEC Test Methods
Table 5-9 Lot Acceptance Tests for GaAs Integrated Circuits
Table 5-10 Lot Acceptance Tests for Discrete GaAs
              Semiconductors
Table 6-1 Data Collection and Trouble Indications
Table C-1 Typical Examination and Tests for Qualification
              Approval (QA)/Quality Conformance (QC)
Table C-2 Typical Test Plan: Qualification Approval (QA)
              and Quality Conformance (QC)
Table C-3 Typical Format Used For Qualification Approval
              (QA)/Quality Conformance (QC) Test Schedule

Gives Bellcore's view of minimum generic component reliability requirements that are currently appropriate for products and equipment used in the network of a typical Bellcore Client Company. Requirements contained within this document apply to all components embedded in a system, including those selected and used by the equipment manufacturer.

DevelopmentNote
Supersedes TA-NWT-000357 Issue 3, Included in DP-357, FR-357, FR-796. (02/2001) Included in FR-2063 and FR-376 (05/2001)
DocumentType
Standard
PublisherName
Telcordia Technologies
Status
Superseded
Supersedes

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SR 3645 : ISSUE 1 COMPENDIUM OF REQUIREMENTS FOR THE USER INTERFACE TO TELEPHONE NETWORK EQUIPMENT
TA NWT 000983 : ISSUE 2 RELIABILITY ASSURANCE PRACTICES FOR OPTOELECTRONIC DEVICES IN LOOP APPLICATIONS
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