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IPC 9703 : 0

Superseded

Superseded

A superseded Standard is one, which is fully replaced by another Standard, which is a new edition of the same Standard.

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superseded

A superseded Standard is one, which is fully replaced by another Standard, which is a new edition of the same Standard.

IPC/JEDEC MECHANICAL SHOCK TEST GUIDELINES FOR SOLDER JOINT RELIABILITY

Available format(s)

Hardcopy

Superseded date

11-08-2019

Language(s)

English

1 SCOPE
2 APPLICABLE DOCUMENTS
  2.1 IPC
  2.2 American Society for Testing and Materials
3 TERMS AND DEFINITIONS
4 USE CONDITIONS OVERVIEW
  4.1 Scope and Application of UCs
  4.2 Capturing UC Data
  4.3 Methods for Developing UCs
      4.3.1 Approach 1 - UC Derivation Approach
      4.3.2 Approach 2 - Leveraging Existing Data to
            Usage Model
      4.3.3 Torture Tests
5 SYSTEM TESTS
  5.1 Shock Test Equipment
      5.1.1 Drop Testers
      5.1.2 Shock Machines
      5.1.3 Inclined Impact
      5.1.4 Fixturing
  5.2 Correlation Criteria
      5.2.1 Unpackaged System Input Correlated to
            Packaged System Environment
      5.2.2 Unpackaged System Input Correlated to
            End User Use-Conditions
  5.3 Test Recommendations
      5.3.1 Testing Sample Recommendations
  5.4 Test Flow
      5.4.1 Packaged System Testing
      5.4.2 Unpackaged System Testing
  5.5 Post Test Analysis
  5.6 Testing Output and Report Recommendations
      5.6.1 General Considerations
      5.6.2 Electrical Testing
      5.6.3 Failure Analysis Considerations
      5.6.4 Reporting Recommendations for Test
            Development
6 SYSTEM BOARD LEVEL TESTING
  6.1 Board Testing Background
  6.2 System Board Testing Recommendations
  6.3 Correlation Criteria and Validity of Test Setup
  6.4 Equipment Recommendations
  6.5 Test Flows
  6.6 Failure Analysis
  6.7 Reporting Recommendations
7 COMPONENT MECHANICAL SHOCK ASSESSMENT
  7.1 Component Assessment - General Considerations
  7.2 Component Board Testing Recommendations
  7.3 Correlation Criteria and Validity of Test Setup
  7.4 Equipment Recommendations
  7.5 Testing Flows
      7.5.1 Characterization Testing
      7.5.2 Qualification Testing
  7.6 Failure Analysis
  7.7 Reporting Recommendations
8 METRICS FOR MATCHING TEST
      8.1.1 Acceleration Based Method
      8.1.2 Board Strain Based Method
Annex A - Sample Data Reporting Format
Annex B - Metrologies
Annex C - Shock Failure Analysis of Electronic Components
Annex D - Suggestions for Selecting Sample Size
Annex E - Suggestions for Finite Element Analysis in
          Mechanical Shock

Describes mechanical drop and shock and test guidelines for assessing solder joint reliability of printed board assemblies from system to component level. Also addresses methods to define mechanical shock use-conditions, methods to define system level, system printed board level and component test board level testing that correlate to such use conditions and guidance on the use of experimental metrologies for mechanical shock tests.

DevelopmentNote
Included in the IPC C 103 & IPC C 1000. (05/2016) Jointly published by IPC and JEDEC. (01/2018)
DocumentType
Standard
Pages
48
PublisherName
Institute of Printed Circuits
Status
Superseded
SupersededBy

IPC 9704 CHINESE : - PRINTED WIRING BOARD STRAIN GAGE TEST GUIDELINE
BS EN 61189-5-1:2016 Test methods for electrical materials, printed boards and other interconnection structures and assemblies General test methods for materials and assemblies. Guidance for printed board assemblies
EN 61189-5-1:2016 Test methods for electrical materials, printed boards and other interconnection structures and assemblies - Part 5-1: General test methods for materials and assemblies - Guidance for printed board assemblies
IEC PAS 62647-3:2011 Process management for avionics - Aerospace and defence electronic systems containing lead-free solder - Part 3: Performance testing for systems containing lead-free solder and finishes
IEC TS 62647-3:2014 Process management for avionics - Aerospace and defence electronic systems containing lead-free solder - Part 3: Performance testing for systems containing lead-free solder and finishes
GEIA STD 0005-3 : 2013 PERFORMANCE TESTING FOR AEROSPACE AND HIGH PERFORMANCE ELECTRONIC INTERCONNECTS CONTAINING PB-FREE SOLDER AND FINISHES
IPC 9707 : 0 SPHERICAL BEND TEST METHOD FOR CHARACTERIZATION OF BOARD LEVEL INTERCONNECTS
IEC 61189-5-1:2016 Test methods for electrical materials, printed boards and other interconnection structures and assemblies - Part 5-1: General test methods for materials and assemblies - Guidance for printed board assemblies
PD IEC/TS 62647-3:2014 Process management for avionics. Aerospace and defence electronic systems containing lead-free solder Performance testing for systems containing lead-free solder and finishes
DD IEC PAS 62647-3 : DRAFT SEP 2011 PROCESS MANAGEMENT FOR AVIONICS - AEROSPACE AND DEFENCE ELECTRONIC SYSTEMS CONTAINING LEAD-FREE SOLDER - PART 3: PERFORMANCE TESTING FOR SYSTEMS CONTAINING LEAD-FREE SOLDER AND FINISHES
IPC 9704 : A PRINTED CIRCUIT ASSEMBLY STRAIN GAGE TEST GUIDELINE

IPC 9252 : A REQUIREMENTS FOR ELECTRICAL TESTING OF UNPOPULATED PRINTED BOARDS
IPC 6012 : C QUALIFICATION AND PERFORMANCE SPECIFICATION FOR RIGID PRINTED BOARDS

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