IEC PAS 62084:1998

1 SCOPE
    1.1 Purpose
    1.2 Categorization
2 TECHNOLOGY OVERVIEW
    2.1 History of Flip Chip
    2.2 Introduction to Chip Scale Packaging
3 APPLICATIONS OF FLIP CHIP AND CHIP SCALE
4 DESIGN CONSIDERATIONS
    4.1 Chip Size Standardization
    4.2 General Considerations for Flip Chips
    4.3 General Consideration for Chip Scale
    4.4 Substrate Structure Standard Grid Evolution
    4.5 Design Output Requirements
    4.6 Electrical Design
    4.7 Thermal Design
5 MATERIAL PROPERTIES AND PROCESSES
    5.1 Solder Bumping
    5.2 Conductive Adhesives
    5.3 Solder Bump Evaluation
    5.4 Other Bumping Techniques and Materials
    5.5 Chip Materials
    5.6 Other Bumping Process Considerations
    5.7 Handling, Shipping and Storage
6 MOUNTING AND INTERCONNECTION STRUCTURES
    6.1 Background
    6.2 Mounting Structures General Considerations
    6.3 Interconnection Substrate Material Choices
    6.4 Surface Finish Properties
    6.5 Substrate Constructions
    6.6 Thermal Requirements
7 ASSEMBLY PROCESSES
    7.1 Substrate Preparation
    7.2 Chip and Chip Scale Placement
    7.3 Attachment Processes
    7.4 Cleaning
    7.5 Attachment Inspection
    7.6 Underfill (Flip Chip Encapsulation)
    7.7 Electrical Test
    7.8 Rework
8 FLIP CHIP TEST AND BURN-IN METHODOLOGY
    8.1 Known Good Die
    8.2 KGD Techniques for Flip Chip
    8.3 Known-Good Mounting and Interconnection Structure
    8.4 Product Verification
9 REQUIREMENTS FOR RELIABILITY
    9.1 Robustness of Products to Use
    9.2 Reliability Factors
    9.3 Reliability Testing
    9.4 DESIGN FOR RELIABILITY (DfR)
10 STANDARDIZATION
    10.1 Standards for Development
    10.2 Flip Chip Development and Performance Standards
    10.3 Standard on Mounting on Substrate Design and
          Performance
    10.4 Flip Chip/Substrate Assembly Design and Performance
          Standards
    10.5 Standards for Material Performance
11 FUTURE NEEDS
    11.1 Critical Factor: Manufacturing Infrastructures
    11.2 Critical Factor: Bump Attachment and Bonding
    11.3 Critical Factor: Testing Scenarios
    11.4 Total Quality Management and Manufacturing
          (TQMM)
Figures
Figure 2-1 Basic Metallurgy/Glass Design for SLT
             Transistors
Figure 2-2 Chip Collapse and Edge Shorting Problem During
             Solder Reflow Joining and Two Solutions
Figure 2-3 Flip Chip with Silver Bump Stand-Off
Figure 2-4 Thick Film Glass Dam Preventing Solder Flow
             and Collapse in First C4 Application
Figure 2-5 Early IBM Hybrid Thick Film Module Mixing Copper
             Ball SMT Transistors and C4 Integrated Circuit
             (12 mm)
Figure 2-6 Thin Film Chromium-Copper-Chromium on Ceramic
             (MC)
Figure 2-7 Cross-Section of Cofired Alumina Multilayer
             Ceramic Package
Figure 2-8 Full Area Array C4 Configuration Microprocessor
             with 762 Solder Bumps in a 29x29 Array
Figure 2-9 Depopulated C4 Array on Chip
Figure 2-10 Area Array C4 Configuration (a) 11x11 Full Array
             with Cantilevered Silicon, (b) SEM View
Figure 2-11 Structure of Hybrid IC Using Solder Bump and
             Cross-Sections
Figure 2-12 Uncapped 50 mm Multi-Chip Module (MCM)
Figure 2-13 IBM Thermal Conduction Module with 100-130
             Flip Chips and Hat with Piston Assemblies
Figure 2-14 Effect of TCE Mismatch on Solder Fatigue Life
Figure 2-15 AT&T Silicon-on-Silicon Packaging System
Figure 2-16 Cut-away of IBM Glass/Ceramic TCM with Polymide/
             Thin Film Surface Redistribution Layer
Figure 2-17 C4 Life Extension by Use of Filled Epoxy Resins
             with Matching Expansivity (Hitachi)
Figure 2-18 IBM SLC Chip-on-Card Technology
Figure 2-19 Bridging the Gap
Figure 2-20 Chip Scale Grid Array Package (CSP-A)
Figure 2-21 Example of Chip Scale
Figure 2-22 Micro BGA
Figure 2-23 Mini BGA
Figure 2-24 SLICC Chip Scale Grid Array
Figure 2-25 Chip Scale Package
Figure 2-26 Resin Encapsulated LSI Chip with Bumps
Figure 2-27 Peripheral Area Array Converter
Figure 2-28 Cutaway View of an MSMT Packaged IC
Figure 2-29 MSMT Posts in Saw Lane
Figure 2-30 MSMT Posts in Bonding Pad Area
Figure 2-31 Cross-Sectional View of an MSMT Package
Figure 2-32 Close-up Photo of MSMT Posts, Encapsulant and
             Bottom of the Chip
Figure 2-33 Chip Scale Peripheral Package
Figure 4-1 Flip Chip Connection
Figure 4-2 Mechanical and Electrical Connections
Figure 4-3 Joined Chip with Chip Underfill
Figure 4-4 A Solder Bump Flip Chip Connection
Figure 4-5 Two Simple Chips, Showing Original Pad Locations
             and Rerouted Bumps
Figure 4-6 Redistribution of a Single Metal Layer Device
Figure 4-7 Passivation (Cross-Section)
Figure 4-8 Schematic Plan View of Bump
Figure 4-9 Example of Pad Limiting Metal
Figure 4-10 Initial C4 Bump
Figure 4-11 A C4 Bump After Reflow
Figure 4-12 Recommended DCA Grid Pitch (250 microns Grid,
             150 microns Bumps)
Figure 4-13 Interconnect Density (Peripheral vs. Area Array)
Figure 4-14 Alpha Particle Emission Track and E/H Pairs
Figure 4-15 Distortion of Depletion by Alpha Particles
Figure 4-16 Chip Edge and Polyimid Seal
Figure 4-17 MSMT Post Configurations
Figure 4-18 Standard Grid Structure
Figure 4-19 Bump Footprint Planning
Figure 4-20 Alignment to Visual/Sensitive Chip Structures
Figure 4-21 Minimum Pitch from Bump to Passivation Seal
             ("A"-half 1/2 finished bump diameter, plus
             alignment to tolerances, plus desired minimum)
Figure 4-22 Redundant Footprint
Figure 4-23 Design Shrink Footprint
Figure 4-24 Signal and Power Distribution Position
Figure 4-25 Nested I/O Footprints
Figure 4-26 Typical Bump Passivation Reticle Mask Format
Figure 4-27 Product Unit Cell Plan (example)
Figure 4-28 Printed Board Flip Chip or Grid Array Land
             Patterns
Figure 4-29 MSMT Land Drawing and Dimensions
Figure 4-30 Bump Electrical Path (Redistributed Chip)
Figure 4-31 Bump Equivalent Circuit (Redistributed Chip)
Figures 4-32 - Figures 10-20
Tables
Table 3-1 Commercial Flip Chip and Chip Scale Applications
Table 3-2 Comparative Table of Various Technologies for a
             100 Lead 10x10 mm Die
Table 4-1 Commonly Used PLM Systems
Table 4-2 C4 Bump Diameter and Minimum Pitch Options
Table 4-3 Alpha Particle Emissions of Semiconductor
             Materials
Table 4-4 Chip Edge Seal Dimensions (Typical)
Table 4-5 Design Rules for Substrates for Chip Scale
             Technology
Table 4-6 Terminal Via and Final Metal Via Pitch
Table 4-7 Final Metal Signal Trace (30 microns)
Table 4-8 Final Metal Power Trace (60 microns)
Table 4-9 Typical Thermal Resistance for Variable Bump
             Options (Triple Layer Chip)
Table 4-10 Typical Bump (150 microns) Thermal Resistances
             Multi-Layer Metal Chips
Table 6-1 Comparison of Selected Material Properties
Table 6-2 Inorganic Substrate Characteristics
Table 9-1 Product Categories and Use Environments
Table 9-2 Coefficients of Thermal Expansion
Table 9-3 Typical Heights (Joined)
Table 9-4 Acceleration Factor Values for Example 1
Table 9-5 Representative Realistic Worse Case Use
             Environments for Surface Mounted Electronics
             and Recommended Accelerated Testing for Surface
             Mount Attachments by Most Common Use Categories