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IPC J STD 012 : 0

Superseded

Superseded

A superseded Standard is one, which is fully replaced by another Standard, which is a new edition of the same Standard.

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superseded

A superseded Standard is one, which is fully replaced by another Standard, which is a new edition of the same Standard.

IMPLEMENTATION OF FLIP CHIP AND CHIP SCALE TECHNOLOGY

Available format(s)

Hardcopy

Superseded date

10-01-2013

Language(s)

English

1 SCOPE
   1.1 Purpose
   1.2 Categorization
2 TECHNOLOGY OVERVIEW
   2.1 History of Flip Chip
   2.2 Introduction to Chip Scale Packaging
3 APPLICATIONS OF FLIP CHIP AND CHIP SCALE
4 DESIGN CONSIDERATIONS
   4.1 Chip Scale Standardization
   4.2 General Considerations for Flip Chips
   4.3 General Considerations for Chip Scale
   4.4 Substrate Structure Standard Grid Evolution
   4.5 Design Output Requirements
   4.6 Electrical Design
   4.7 Thermal Design
5 MATERIAL PROPERTIES AND PROCESSES
   5.1 Solder Bumping
   5.2 Conductive Adhesives
   5.3 Solder Bump Evaluation
   5.4 Other Bumping Techniques and Materials
   5.5 Chip Materials
   5.6 Other Bumping Process Considerations
   5.7 Handling, Shipping and Storage
6 MOUNTING AND INTERCONNECTION STRUCTURES
   6.1 Background
   6.2 Mounting Structures General Considerations
   6.3 Interconnection Substrate Material Choices
   6.4 Surface Finish Properties
   6.5 Substrate Constructions
   6.6 Thermal Requirements
7 ASSEMBLY PROCESSES
   7.1 Substrate Preparation
   7.2 Chip and Chip Scale Placement
   7.3 Attachment Processes
   7.4 Cleaning
   7.5 Attachment Inspection
   7.6 Underfill (Flip Chip Encapsulation)
   7.7 Electrical Test
   7.8 Rework
8 FLIP CHIP TEST AND BURN-IN METHODOLOGY
   8.1 Known Good Die
   8.2 KGD Techniques for Flip Chip
   8.3 Known-Good Mounting and Interconnection Structure
   8.4 Product Verification
9 REQUIREMENTS FOR RELIABILITY
   9.1 Robustness of Product to Use
   9.2 Reliability of Factors
   9.3 Reliability Testing
   9.4 Design for Reliability (DfR)
10 STANDARDIZATION
   10.1 Standards for Development
   10.2 Flip Chip Development and Performance Standards
   10.3 Standard on Mounting of Substrate Design and
        Performance
   10.4 Flip Chip/Substrate Assembly Design and Performance
        Standards
   10.5 Standards for Material Performance
11 FUTURE NEEDS
   11.1 Critical Factor: Manufacturing Infrastructure
   11.2 Critical Factor: Bump Attachment and Bonding
   11.3 Critical Factor: Testing Scenarios
   11.4 Total Quality Management and Manufacturing (TQMM)
Figures
Tables

Outlines the implementation of flip chip and related chip scale semiconductor packaging technologies. The areas discussed include: design considerations, assembly processes technology choices, application and reliability data. Chip packaging variations include: flip chip, HDI, Micro BGA, Micro SMT and SLICC. This is intended to provide general information on implementing flip chip and chip scale technologies for creating multichip modules, I/C cards, memory cards and very dense surface mount assemblies.

DevelopmentNote
Included in IPC C 103 & IPC C 1000. (08/2008)
DocumentType
Standard
Pages
120
PublisherName
Institute of Printed Circuits
Status
Superseded
SupersededBy

Standards Relationship
IEC PAS 62084:1998 Identical

BS EN 62258-1:2010 Semiconductor die products Procurement and use
I.S. EN 62258-1:2010 SEMICONDUCTOR DIE PRODUCTS - PART 1: PROCUREMENT AND USE
EN 62258-1:2010 Semiconductor die products - Part 1: Procurement and use
IPC CM 770 : E COMPONENT MOUNTING GUIDELINES FOR PRINTED BOARDS
IPC AJ 820 : A ASSEMBLY AND JOINING HANDBOOK
IPC SM 784 : 0 GUIDELINES FOR CHIP-ON-BOARD TECHNOLOGY IMPLEMENTATION
IPC J STD 013 : 0 IMPLEMENTATION OF BALL GRID ARRAY AND OTHER HIGH DENSITY TECHNOLOGY
IPC J STD 027 : 0 MECHANICAL OUTLINE STANDARD FOR FLIP CHIP AND CHIP SIZE CONFIGURATIONS
IPC J STD 026 : 0 SEMICONDUCTOR DESIGN STANDARD FOR FLIP CHIP APPLICATIONS
IPC J STD 028 : 0 PERFORMANCE STANDARD FOR CONSTRUCTION OF FLIP CHIP AND CHIP SCALE BUMPS
IEC 62258-1:2009 Semiconductor die products - Part 1: Procurement and use
CEI EN 62258-1 : 2011 SEMICONDUCTOR DIE PRODUCTS - PART 1: PROCUREMENT AND USE

IPC SM 784 : 0 GUIDELINES FOR CHIP-ON-BOARD TECHNOLOGY IMPLEMENTATION
IPC J STD 026 : 0 SEMICONDUCTOR DESIGN STANDARD FOR FLIP CHIP APPLICATIONS
IEC PAS 62085:1998 Implementation of ball grid array and other high density technology
IPC J STD 013 : 0 IMPLEMENTATION OF BALL GRID ARRAY AND OTHER HIGH DENSITY TECHNOLOGY
IPC J STD 028 : 0 PERFORMANCE STANDARD FOR CONSTRUCTION OF FLIP CHIP AND CHIP SCALE BUMPS
IPC WP 003 : 1993 CHIP MOUNTING TECHNOLOGY (CMT)
IPC M 103 : LATEST STANDARDS FOR SURFACE MOUNT ASSEMBLIES MANUAL

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